参数资料
| 型号： | ADV601LCJSTZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 3/44页 |
| 文件大小： | 0K |
| 描述： | IC CODEC VIDEO DSP/SRL 120LQFP |
| 标准包装： | 1 |
| 类型： | 视频编解码器 |
| 数据接口： | DSP，串行 |
| 分辨率（位）： | 8 b |
| 三角积分调变： | 无 |
| 电压 - 电源，模拟： | 4.5 V ~ 5.5 V |
| 电压 - 电源，数字： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 120-LQFP |
| 供应商设备封装： | 120-LQFP（14x14） |
| 包装： | 托盘 |
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ADV601LC
–11–
REV. 0
[4]
FIFO Error, FIFOERR. This condition indicates that the host has been unable to keep up with the ADV601LC’s compressed
data supply or demand requirements. If this condition occurs during encode, the data stream will not be corrupted until
MERR indicates that the DRAM is also overflowed. If this condition occurs during decode, the video output will be
corrupted. If the system overflows the FIFO (disregarding a FIFOSTP condition) with too many writes in decode mode,
FIFOERR is asserted. This read only status bit indicates the following:
0
No FIFO Error condition, reset value (FIFO_ERR pin LO)
1
FIFO overflow (encode) or underflow (decode) (FIFO_ERR pin HI)
[5]
FIFO Stop, FIFOSTP. This condition indicates that the FIFO is full in decode mode and empty in encode mode.
In decode mode only, FIFOSTP status actually behaves more conservatively than this. In decode mode, even when
FIFOSTP is indicated, there are still 32 empty Dwords available in the FIFO and 32 more Dword writes can safely
be performed. This status bit indicates the following:
0
No FIFO Stop condition, reset value (FIFO_STP pin LO)
1
FIFO empty (encode) or full (decode) (FIFO_STP pin HI)
[6]
Memory Error, MERR. This condition indicates that an error has occurred at the DRAM memory interface. This condition can
be caused by a defective DRAM, the inability of the Host to keep up with the ADV601LC compressed data stream, or bit errors
in the data stream. Note that the ADV601LC recovers from this condition without host intervention.
0
No memory error condition, reset value
1
Memory error
[7]
Reserved (always read/write zero)
[8]
Interrupt Enable on CCIRER, IE_CCIRER. This mask bit selects the following:
0
Disable CCIR-656 data error interrupt, reset value
1
Enable interrupt on error in CCIR-656 data
[9]
Interrupt Enable on STATR, IE_STATR. This mask bit selects the following:
0
Disable Statistics Ready interrupt, reset value
1
Enable interrupt on Statistics Ready
[10]
Interrupt Enable on LCODE, IE_LCODE. This mask bit selects the following:
0
Disable Last Code Read interrupt, reset value
1
Enable interrupt on Last Code Read from FIFO
[11]
Interrupt Enable on FIFOSRQ, IE_FIFOSRQ. This mask bit selects the following:
0
Disable FIFO Service Request interrupt, reset value
1
Enable interrupt on FIFO Service Request
[12]
Interrupt Enable on FIFOERR, IE_FIFOERR. This mask bit selects the following:
0
Disable FIFO Stop interrupt, reset value
1
Enable interrupt on FIFO Stop
[13]
Interrupt Enable on FIFOSTP, IE_FIFOSTP. This mask bit selects the following:
0
Disable FIFO Error interrupt, reset value
1
Enable interrupt on FIFO Error
[14]
Interrupt Enable on MERR, IE_MERR. This mask bit selects the following:
0
Disable memory error interrupt, reset value
1
Enable interrupt on memory error
[15]
Reserved (always read/write zero)
Mode Control Register
Indirect (Write Only) Register Index 0x00
This register holds configuration data for the ADV601LC’s video interface format and controls several other video interface features.
For more information on formats and modes, see the Video Interface section. Bits in this register have the following functions:
[3:0]
Video Interface Format, VIF[3:0]. These bits select the interface format. Valid settings include the following (all
other values are reserved):
0x0
CCIR-656, reset value
0x2
MLTPX (Philips)
[4]
VCLK Output Divided by two, VCLK2. This bit controls the following:
0
Do not divide VCLK output (VCLKO = VCLK), reset value
1
Divide VCLK output by two (VCLKO = VCLK/2)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADV601LCJSTZRL | 功能描述:IC CODEC VIDEO DSP/SRL 120LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 编解码器 系列:- 标准包装:2,500 系列:- 类型:立体声音频 数据接口:串行 分辨率（位）:18 b ADC / DAC 数量:2 / 2 三角积分调变:是 S/N 比，标准 ADC / DAC (db):81.5 / 88 动态范围，标准 ADC / DAC (db):82 / 87.5 电压 - 电源，模拟:2.6 V ~ 3.3 V 电压 - 电源，数字:1.7 V ~ 3.3 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-WFQFN 裸露焊盘 供应商设备封装:48-TQFN-EP（7x7） 包装:带卷 (TR) |
| ADV601LC-VIDEOPIPE | 制造商:Analog Devices 功能描述:TOOLS:DEVELOPMENT BOARDS H/W 制造商:Analog Devices 功能描述:EVALUATION BOARD ((NS)) |
| ADV601XS | 制造商:Analog Devices 功能描述: |
| ADV611 | 制造商:AD 制造商全称:Analog Devices 功能描述:CLOSED CIRCUIT TV DIGITAL VIDEO CODEC |
| ADV611JST | 制造商:Analog Devices 功能描述:Video Compression 120-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:CLOSED CIRCUIT TV VIDEO CODEC - TQFP PKG - Tape and Reel |
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