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| 型号： | AFE7222IRGCR |
| 厂商： | Texas Instruments |
| 文件页数： | 24/106页 |
| 文件大小： | 0K |
| 描述： | IC AFE 12BIT 65/130MSPS 64VQFN |
| 标准包装： | 2,000 |
| 位数： | 12 |
| 通道数： | 4 |
| 功率（瓦特）： | 610mW |
| 电压 - 电源，模拟： | 2.85 V ~ 3.6 V |
| 电压 - 电源，数字： | 1.7 V ~ 1.9 V |
| 封装/外壳： | 64-VFQFN 裸露焊盘 |
| 供应商设备封装： | 64-VQFN 裸露焊盘（9x9） |
| 包装： | 带卷 (TR) |
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SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
Register Name – CONFIG5 – Address 0x108, Default = 0x00
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
Tx_INV_SINC_FIL_EN_SRC
Tx_INV_SINC_FIL_EN
TX_DIV_PHASE_
TX_DIV_PHASE(1:0)
TX_DATA_ROUTE_
INCR
ORDER (1:0)
TX_DATA_ROUTE_ORDER (1:0) – Specifies the order in which the A and B outputs of the TX Signal
Chain are routed to the DACs
VALUE
ROUTING ORDER
0
Normal – DACA gets TX Output A and DACB gets TX Output B
1
Both DACs get TX Output A
2
Both DACs get TX Output B
3
Swapped – DACA gets TX Output B and DACB gets TX Output A
TX_DIV_PHASE (1:0) – The value programmed into this is applied as the TX Divider phase, when the
divider is synced. The divider here refers to the clock divider that divides the DAC_CLK depending on the
interpolation factor. For division by 2, there are 2 possible phases of the divided clock. For division by 4,
there are 4 possible phases. If the divider phase is not synced across chips, then it will cause a phase
uncertainty in the DAC analog output, and can also cause uncertainty in the CMIX operation.
TX_DIV_PHASE_INCR – This bit is a method to control the phase of the divided clock without using the
SYNC pin. A 0 to 1 transition on this bit causes the phase of division in the TX Divider to be incremented
by 1 with respect to the current phase of division. To increment the phase of division more than once,
clear and then set this bit once again. Global syncing as well as Syncing for the Tx Divider needs to be
disabled for this mode to work.
Tx_INV_SINC_FIL_EN – Enables the Tx Inverse Sinc Filter. Set Tx_INV_SINC_FIL_EN_SRC for this to
take effect.
Tx_INV_SINC_FIL_EN_SRC – When set, this allows Tx_INV_SINC_FIL_EN to take effect.
Register Name – CONFIG6 – Address 0x10B, Default = 0x00
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TX_CMIX_SYNC_
TX_GLOBAL_
TX_QMC_GAIN_PH_
TX_QMC_OFF_
TX_DIV_
TX_CMIX_
TX_FIFO_
SRC
SYNC_DIS
TX_FIFO_SYNC_DIS
–
Disables
Syncing
of
the
FIFO.
This
takes
effect
only
when
TX_GLOBAL_SYNC_DIS is set. This is only a enable/ disable bit – the actual sync source can be set to
pin or serial interface. When the FIFO is synced, the read and write pointers are initialized such that they
are separated by 4 positions.This mode is common for both channels.
TX_CMIX_SYNC_DIS
–
Disables
Syncing
of
the
Tx
CMIX
.This
takes
effect
only
when
TX_GLOBAL_SYNC_DIS is set. CMIX syncing refers to setting the phase of the complex mixing. This
mode is common for both channels.
TX_DIV_SYNC_DIS – Disables Syncing of the Tx Divider phase .This takes effect only when
TX_GLOBAL_SYNC_DIS is set. Common for both channels.
TX_QMC_OFF_SYNC_DIS – Disables Syncing of Tx QMC Offset Correction .This takes effect only when
TX_GLOBAL_SYNC_DIS is set. This mode is common for both channels.
TX_QMC_GAIN_PH_SYNC_DIS – Disables Syncing of Tx QMC Gain Phase Correction .This takes effect
only when TX_GLOBAL_SYNC_DIS is set. This mode is common for both channels.
TX_GLOBAL_SYNC_DIS – When set, disables global syncing of TX and enables block level syncing.
When cleared, a rising edge on the selected sync source causes all TX blocks to be synced.
24
REGISTER DESCRIPTIONS
Copyright 2011–2012, Texas Instruments Incorporated
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