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| 型号： | AGLN030V2-FUCG81 |
| 元件分类： | FPGA |
| 英文描述： | FPGA, PBGA81 |
| 封装： | 4 X 4 MM, 0.80 MM HEIGHT, 0.40 MM PITCH, ROHS COMPLIANT, UCSP-81 |
| 文件页数： | 19/114页 |
| 文件大小： | 3991K |
| 代理商： | AGLN030V2-FUCG81 |
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IGLOO nano Device Overview
1- 8
A d vance v0.4
For devices using the six CCC block architecture, these are located at the four corners and the
centers of the east and west sides. All six CCC blocks are usable; the four corner CCCs and the east
CCC allow simple clock delay operations as well as clock spine access.
The inputs of the six CCC blocks are accessible from the FPGA core or from dedicated connections
to the CCC block, which are located near the CCC.
The CCC block has these key features:
Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz
Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz
2 programmable delay types for clock skew minimization
Clock frequency synthesis (for PLL only)
Additional CCC specifications:
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output
divider configuration (for PLL only).
Output duty cycle = 50% ± 1.5% or better (for PLL only)
Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single
global network used (for PLL only)
Maximum acquisition time is 300 s (for PLL only)
Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL
only)
Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /
fOUT_CCC (for PLL only)
Global Clocking
IGLOO nano devices have extensive support for multiple clocking domains. In addition to the CCC
and PLL support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three
quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the
core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for
rapid distribution of high-fanout nets.
I/Os with Advanced I/O Standards
IGLOO nano FPGAs feature a flexible I/O structure, supporting a range of voltages (1.2 V, 1.5 V,
1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V).
The I/Os are organized into banks with two, three, or four banks per device. The configuration of
these banks determines the I/O standards supported.
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of various single-data-rate applications for all versions of nano devices and
double-data-rate applications for the AGLN060, AGLN125, and AGLN250 devices.
IGLOO nano devices support LVTLL and LVCMOS I/O standards, are hot-swappable, and support
cold-sparing and Schmitt trigger.
Wide Range I/O Support
Actel nano devices support JEDEC-defined wide range I/O operation. IGLOO nano devices support
both the JESD8-B specification, covering both 3 V and 3.3 V supplies, for an effective operating
range of 2.7 V to 3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating
range of 1.14 V to 1.575 V.
Wider I/O range means designers can eliminate power supplies or power conditioning components
from the board or move to less costly components with greater tolerances. Wide range eases I/O
bank management and provides enhanced protection from system voltage spikes, while providing
the flexibility to easily run custom voltage applications.
相关PDF资料 |
PDF描述 |
|---|---|
| AGLN030V2-FVQ100 | FPGA, PQFP100 |
| AGLN030V2-FVQG100 | FPGA, PQFP100 |
| AGLN030V2-ZFCS81 | FPGA, PBGA81 |
| AGLN030V2-ZFCSG81 | FPGA, PBGA81 |
| AGLN030V2-ZFQN48 | FPGA, PQCC48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AGLN030V2-ZCSG81 | 功能描述:IC FPGA NANO 1KB 30K 81-CSP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:IGLOO nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14） |
| AGLN030V2-ZCSG81I | 功能描述:IC FPGA NANO 1KB 30K 81-CSP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:IGLOO nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14） |
| AGLN030V2-ZQNG48 | 功能描述:IC FPGA NANO 1KB 30K 48-QFN RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:IGLOO nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14） |
| AGLN030V2-ZQNG48I | 功能描述:IC FPGA NANO 1KB 30K 48-QFN RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:IGLOO nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14） |
| AGLN030V2-ZQNG68 | 功能描述:IC FPGA NANO 1KB 30K 68-QFN RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:IGLOO nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14） |
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