参数资料
型号: AGLN030V2-FUCG81
元件分类: FPGA
英文描述: FPGA, PBGA81
封装: 4 X 4 MM, 0.80 MM HEIGHT, 0.40 MM PITCH, ROHS COMPLIANT, UCSP-81
文件页数: 95/114页
文件大小: 3991K
代理商: AGLN030V2-FUCG81
IGLOO nano DC and Switching Characteristics
Ad vance v0.2
2-67
Table 2-93 IGLOO nano CCC/PLL Specification
For IGLOO nano V2 Devices, 1.2 V DC Core Supply Voltage
Parameter
Min.
Typ.
Max.
Units
Clock Conditioning Circuitry Input Frequency fIN_CCC
1.5
160
MHz
Clock Conditioning Circuitry Output Frequency fOUT_CCC
0.75
160
MHz
Delay Increments in Programmable Delay Blocks 1, 2
580
ps
Number of Programmable Values in Each Programmable Delay Block
32
Serial Clock (SCLK) for Dynamic PLL 5
60
MHz
Input Cycle-to-Cycle Jitter (peak magnitude)
0.25
ns
CCC Output Peak-to-Peak Period Jitter FCCC_OUT
Max Peak-to-Peak Period Jitter
1 Global
Network
Used
External
FB Used
3 Global
Networks
Used
0.75 MHz to 24 MHz
0.50%
0.75%
0.70%
24 MHz to 100 MHz
1.00%
1.50%
1.20%
100 MHz to 160 MHz
2.50%
3.75%
2.75%
Acquisition Time
LockControl = 0
300
s
LockControl = 1
6.0
ms
Tracking Jitter
LockControl = 0
4
ns
LockControl = 1
3
ns
Output Duty Cycle
48.5
51.5
%
Delay Range in Block: Programmable Delay 1 1, 2
2.3
20.86
ns
Delay Range in Block: Programmable Delay 2 1, 2,
0.025
20.86
ns
Delay Range in Block: Fixed Delay 1, 2
5.7
ns
Notes:
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-7
for deratings.
2. TJ = 25°C, VCC = 1.2 V
3. The AGLN010, AGLN015, and AGLN020 devices do not support PLLs.
4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input
clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by period
jitter parameter.
5. Maximum value obtained for a STD speed grade device in Worst-Case Commercial conditions. For specific
junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 and Table 2-7 on page 2-7
for derating values.
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