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参数资料
| 型号： | AM29DL162CB120ZEN |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 1M X 16 FLASH 3V PROM, 120 ns, PDSO56 |
| 封装： | SSOP-56 |
| 文件页数： | 20/55页 |
| 文件大小： | 775K |
| 代理商： | AM29DL162CB120ZEN |
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September 7, 2007 21533C2
Am29DL16xC
25
D A TA
SH EE T
Figure 3.
Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 14
shows the address and data requirements for the chip
erase command sequence.
When the Embedded Erase algorithm is complete,
that bank returns to reading array data and addresses
are no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6,
DQ2, or RY/BY#. Refer to the Write Operation Status
section for information on these status bits.
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that oc-
curs, the chip erase command sequence should be
reinitiated once that bank has returned to reading
array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations ta-
bles in the AC Characteristics section for parameters,
and Figure 19 section for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Table 14 shows the ad-
dress and data requirements for the sector erase com-
mand sequence.
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 s occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than
50 s, otherwise erasure may begin. Any sector erase
address and command following the exceeded
time-out may or may not be accepted. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector
Erase command is written. Any command other than
Sect or Era se or Era se Sus p end d u ri ng the
time-out period resets that bank to reading array
data. The system must rewrite the command se-
quence and any additional addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out (See the section on DQ3: Sector
Erase Timer.). The time-out begins from the rising edge of
the final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the
bank returns to reading array data and addresses are
no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read
data from the non-erasing bank. The system can de-
termine the status of the erase operation by reading
DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer
to the Write Operation Status section for information
on these status bits.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data?
No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
Note: See Table 14 for program command sequence.
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相关代理商/技术参数 |
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| AM29DL163DB-90EI\\T | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 16MBIT 2MX8/1MX16 90NS 48TSOP - Tape and Reel |
| AM29DL163DB-90EI\T | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 16MBIT 2MX8/1MX16 90NS 48TSOP - Tape and Reel |
| AM29DL163DB-90EIT | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 16MBIT 2MX8/1MX16 90NS 48TSOP - Tape and Reel |
| AM29DL163DT70EF | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 16MBIT 2MX8/1MX16 70NS 48TSOP - Trays |
| AM29DL163DT-70EF | 制造商:Spansion 功能描述: |
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