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| 型号： | AM29DS323DT120 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation Flash Memory |
| 中文描述： | 32兆位（4个M × 8位/ 2米x 16位），1.8伏的CMOS只，同时作业快闪记忆体 |
| 文件页数： | 19/54页 |
| 文件大小： | 1013K |
| 代理商： | AM29DS323DT120 |
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Am29DS323D
25
P R E L I M I NARY
The system must write the reset command to return to
reading array data (or erase-suspend-read mode if the
bank was previously in Erase Suspend).
Enter SecSi
TM Sector/Exit SecSi Sector
Command Sequence
The system can access the SecSi Sector region by is-
suing the three-cycle Enter SecSi Sector command
sequence. The device continues to access the SecSi
Sector region until the system issues the four-cycle
Exit SecSi Sector command sequence. The Exit SecSi
Sector command sequence returns the device to nor-
mal operation. Table 14 shows the address and data
requirements for both command sequences. See also
Memory Region” for further information. Note that a
hardware reset (RESET#=V
IL) will reset the device to
reading array data.
Byte/Word Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Program-
ming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock
write cycles, followed by the program set-up com-
mand. The program address and data are written next,
which in turn initiate the Embedded Program algo-
rithm. The system is
not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Table 14 shows the address
and data requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete,
that bank then returns to reading array data and ad-
dresses are no longer latched. The system can
determine the status of the program operation by
using DQ7, DQ6, or RY/BY#. Refer to the Write Oper-
ation Status section for information on these status
bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated once that bank has returned to reading
array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause that bank to set DQ5 = 1, or cause the DQ7 and
DQ6 status bits to indicate the operation was success-
ful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a “0”
to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram bytes or words to a bank faster than using the
standard program command sequence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write
cycle containing the unlock bypass command, 20h.
That bank then enters the unlock bypass mode. A
two-cycle unlock bypass program command sequence
is all that is required to program in this mode. The first
cycle in this sequence contains the unlock bypass pro-
gram command, A0h; the second cycle contains the
program address and data. Additional data is pro-
grammed in the same manner. This mode dispenses
with the initial two unlock cycles required in the stan-
dard program command sequence, resulting in faster
total programming time. Table 14 shows the require-
ments for the command sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the bank
address and the data 90h. The second cycle need
only contain the data 00h. The bank then returns to
the reading array data.
The device offers accelerated program operations
through the WP#/ACC pin. When the system asserts
V
HH on the WP#/ACC pin, the device automatically en-
ters the Unlock Bypass mode. The system may then
write the two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that
the WP#/ACC pin must not be at V
HH any operation
other than accelerated programming, or device dam-
age may result. In addition, the WP#/ACC pin must not
be left floating or unconnected; inconsistent behavior
of the device may result.
Figure 3 illustrates the algorithm for the program oper-
ation. Refer to the Erase and Program Operations
table in the AC Characteristics section for parameters,
and Figure 17 for timing diagrams.
相关PDF资料 |
PDF描述 |
|---|---|
| AM29DS323DT120EIN | Hex Inverters 14-TSSOP -40 to 85 |
| AM29F017D-120E4C | 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| AM29F017D-120E4E | 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| AM29F017D-120E4I | 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| AM29F017D-120EC | 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AM29F002B-70JC | 制造商:Advanced Micro Devices 功能描述:NOR Flash, 256K x 8, 32 Pin, Plastic, PLCC |
| AM29F002BB-120EC | 制造商:Spansion 功能描述:2M (256KX8) 5V, BOOT BLOCK, BOT, TSOP32, COM - Trays |
| AM29F002BB-120JCT | 制造商:Spansion 功能描述:2M (256KX8) 5V, BOOT BLOCK, BOT, PLCC32, COM, T&R - Tape and Reel |
| AM29F002BB-55EC | 制造商:Spansion 功能描述: |
| AM29F002BB-55JF | 制造商:Spansion 功能描述:NOR Flash Parallel 5V 2Mbit 256K x 8bit 55ns 32-Pin PLCC |
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