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| 型号： | AM29PDL127H85VKI |
| 厂商： | Spansion Inc. |
| 英文描述： | 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control |
| 中文描述： | 128兆位（8米× 16位），3.0伏的CMOS只，页面模式同步读/写闪存与增强VersatileIO控制记忆 |
| 文件页数： | 5/68页 |
| 文件大小： | 750K |
| 代理商： | AM29PDL127H85VKI |
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June 30, 2003
Am29PDL127H
11
ADV ANCE
I N FO RMAT I O N
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1.
Am29PDL127H Device Bus Operations
Legend: L = Logic Low = V
IL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 8.5–9.5 V, X = Don’t Care, SA = Sector Address,
A
IN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the High
Voltage Sector Protection section.
2. WP#/ACC must be high when writing to sectors 0, 1, 268, or 269.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the OE# and appropriate CE# pins to V
IL. CE# is
the power control. OE# is the output control and gates
array data to the output pins. WE# should remain at
V
IH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
Refer to the AC Characteristics table for timing specifi-
cations and to Figure 11 for the timing diagram. I
CC1 in
the DC Characteristics table represents the active cur-
rent specification for reading array data.
Random Read (Non-Page Read)
Address access time (t
ACC) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (t
CE ) is the delay from the stable ad-
dresses and stable CE# to valid data at the output in-
puts. The output enable access time is the delay from
the falling edge of the OE# to valid data at the output
inputs (assuming the addresses have been stable for
at least t
ACC–tOE time).
Page Mode Read
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper-
ation. This mode provides faster read access speed
for random locations within a page. Address bits
A22–A3 select an 8 word page, and address bits
A2–A0 select a specific word within that page. This is
an asynchronous operation with the microprocessor
supplying the specific word location.
The random or initial page access is t
ACC or tCE and
subsequent page read accesses (as long as the loca-
tions specified by the microprocessor falls within that
page) is equivalent to t
PACC. When CE# is deasserted
(CE#=V
IH), the reassertion of CE# for subsequent ac-
Operation
CE#
OE#
WE#
RESET#
WP#/ACC
Addresses
(A22–A0)
DQ15–
DQ0
Read
L
H
X
A
IN
D
OUT
Write
L
H
L
H
X
AIN
DIN
Standby
V
IO±
0.3 V
XX
V
IO ±
0.3 V
X (Note 2)
X
High-Z
Output Disable
L
H
X
High-Z
Reset
X
L
X
High-Z
Temporary Sector Unprotect (High
Voltage)
XX
X
VID
XAIN
DIN
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