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参数资料
| 型号： | AN1406 |
| 厂商： | ON SEMICONDUCTOR |
| 英文描述： | DESIGNING WITH PECL (ECL AT + 5.0) |
| 中文描述： | 具有PECL设计（ECL在5.0） |
| 文件页数： | 2/8页 |
| 文件大小： | 117K |
| 代理商： | AN1406 |
AN1406/D
http://onsemi.com
2
several boards, across relatively large distances, ECL
devices provide the CMOS/TTL designer a means of
ensuring reliable transmission while minimizing EMI
radiation and crosstalk.
Figure 1 shows a typical application in which the long line
driving, high bandwidth capabilities of ECL can be utilized.
The majority of the data processing is done on wide bit width
words with a clock cycle commensurate with the bandwidth
capabilities of CMOS and TTL logic. The parallel data is
then serialized into a high bandwidth data stream, a
bandwidth which requires ECL technologies, for
transmission across a long line to another box or machine.
The signal is received differentially and converted back to
relatively low speed parallel data where it can be processed
further in CMOS/TTL logic. By taking advantage of the
bandwidth and line driving capabilities of ECL the system
minimizes the number of lines required for interconnecting
the subsystems without sacrificing the overall performance.
Furthermore by taking advantage of PECL this application
can be realized with a single five volt power supply. The
configuration of Figure 1 illustrates a situation where the
mixing of logic technologies can produce a design which
maximizes the overall performance while managing power
dissipation and minimizing cost.
Figure 1. Typical Use of ECL’s High Bandwidth,
Line Driving Capabilities
ECL Serial
Data >200MHz
CMOS/TTL Parallel
Data <50MHz
ECL Serial
Data >200MHz
Low Frequency
Information Proces-
sing
Serial/Parallel
Conversion
Parallel/Serial
Conversion
CMOS/TTL Parallel
Data <50MHz
Clock Distribution
Perhaps the most attractive area for ECL in CMOS/ TTL
designs is in clock distribution. The ever increasing
performance capabilities of today’s designs has placed an
even greater emphasis on the design of low skew clock
generation and distribution networks. Clock skew, the
difference in time between “simultaneous” clock transitions
throughout an entire system, is a major component of the
constraints which form the upper bound for the system clock
frequency. Reductions in system clock skew allow designers
to increase the performance of their designs without having
to resort to more complicated architectures or costly, faster
logic. ECL logic has the capability of significantly reducing
the clock skew of a system over an equivalent design
utilizing CMOS or TTL technologies.
The skew introduced by a logic device can be broken up
into three areas; the part–to–part skew, the within–part skew
and the rise–to–fall skew. The part–to–part skew is defined
as the differences in propagation delays between any two
devices while the within–device skew is the difference
between the propagation delays of similar paths for a single
device. The final portion of the device skew is the
rise–to–fall skew or simply the differences in propagation
delay between a rising input and a failing input on the same
gate. The within–device skew and the rise–to–fall skew
combine with delay variations due to environmental
conditions and processing to comprise the part–to–part
skew. The part–to–part skew is defined by the propagation
delay window described in the device data sheets.
Careful attention to die layout and package choice will
minimize within–device skew. Although this minimization
is independent of technology, there are other characteristics
of ECL which will further reduce the skew of a device.
Unlike their CMOS/TTL counterparts, ECL devices are
relatively insensitive to variations in supply voltage and
temperature.
Propagation
environmental conditions must be accounted for in the
specification windows of a device. As a result because of
ECLs AC stability the delay windows for a device will
inherently be smaller than similar CMOS or TTL functions.
The virtues of differential interconnect in line driving
have already been addressed, however the benefits of
differential interconnect are even more pronounced in clock
distribution. The propagation delay of a signal through a
device is intimately tied to the switching threshold of that
device. Any deviations of the threshold from the center of
the input voltage swing will increase or decrease the delay
of the signal through the device. This difference will
manifest itself as rise–to–fall skew in the device. The
threshold levels for both CMOS and TTL devices are a
function of processing, layout, temperature and other factors
which are beyond the control of the system level designer.
Because of the variability of these switching references,
specification limits must be relaxed to guarantee acceptable
manufacturing yields. The level of relaxation of these
specifications increases with increasing logic depth. As the
depth of the logic within a device increases the input signal
will switch against an increasing number of reference levels;
each encounter will add skew when the reference level is not
perfectly centered. These relaxed timing windows add
directly to the overall system skew. Differential ECL, both
internal and external to the die, alleviates this threshold
sensitivity as a DC switching reference is no longer required.
Without the need for a switching reference the delay
windows, and thus system skew, can be significantly
delay
variations
with
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AN1406/D | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:DESIGNING WITH PECL (ECL AT + 5.0) |
| AN1406D | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:3.3V / 5V ECL 2-Input Differential XOR/XNOR |
| AN14-17A | 制造商:AN# - MILITARY 功能描述: |
| AN1431 | 制造商:PANASONIC 制造商全称:Panasonic Semiconductor 功能描述:Surface-mount Adjustable Output Shunt Regulator |
| AN1431M | 功能描述:IC VREF SHUNT ADJ TO-243 RoHS:是 类别:集成电路 (IC) >> PMIC - 电压基准 系列:- 产品培训模块:Voltage Reference Basics 标准包装:100 系列:- 基准类型:旁路，精度 输出电压:4.096V 容差:±0.075% 温度系数:50ppm/°C 输入电压:- 通道数:1 电流 - 阴极:1µA 电流 - 静态:- 电流 - 输出:10mA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:管件 |
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