参数资料
| 型号： | APA300-FGG144I |
| 厂商： | Microsemi SoC |
| 文件页数： | 103/178页 |
| 文件大小： | 0K |
| 描述： | IC FPGA PROASIC+ 300K 144-FBGA |
| 标准包装： | 160 |
| 系列： | ProASICPLUS |
| RAM 位总计： | 73728 |
| 输入/输出数： | 100 |
| 门数： | 300000 |
| 电源电压： | 2.3 V ~ 2.7 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 144-LBGA |
| 供应商设备封装： | 144-FPBGA（13x13） |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页当前第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页
ProASICPLUS Flash Family FPGAs
2- 20
v5.9
User Security
ProASICPLUS devices have FlashLock protection bits that,
once
programmed,
block
the
entire
programmed
contents from being read externally. Refer to Table 2-11
for details on the number of bits in the key for each
device. If locked, the user can only reprogram the device
employing the user-defined security key. This protects
the device from being read back and duplicated. Since
programmed data is stored in nonvolatile memory cells
(actually very small capacitors) rather than in the wiring,
physical deconstruction cannot be used to compromise
data. This type of security breach is further discouraged
by the placement of the memory cells beneath the four
metal layers (whose removal cannot be accomplished
without disturbing the charge in the capacitor). This is
the highest security provided in the industry. For more
information,
refer
to
Actel’s
Nonvolatile Flash and Antifuse FPGAs white paper.
Embedded Memory Floorplan
The embedded memory is located across the top and
bottom of the device in 256x9 blocks (Figure 1-1 on page
1-2). Depending on the device, up to 88 blocks are
available to support a variety of memory configurations.
Each block can be programmed as an independent
memory array or combined (using dedicated memory
routing resources) to form larger, more complex memory
configurations. A single memory configuration could
include blocks from both the top and bottom memory
locations.
Embedded Memory Configurations
The embedded memory in the ProASICPLUS family
provides great configuration flexibility (Table 2-12). Each
ProASICPLUS block is designed and optimized as a two-
port memory (one read, one write). This provides 198
kbits of two-port and/or single port memory in the
APA1000 device.
Each memory block can be configured as FIFO or SRAM,
with
independent
selection
of
synchronous
or
asynchronous
read
and
write
ports
Additional characteristics include programmable flags as
well as parity checking and generation. Figure 2-18 on
page 2-22 and Figure 2-19 on page 2-23 show the block
diagrams of the basic SRAM and FIFO blocks. Table 2-14
on page 2-22 and Table 2-15 on page 2-23 describe
memory
block
SRAM
and
FIFO
interface
signals,
respectively. A single memory block is designed to
operate at up to 150 MHz (standard speed grade typical
conditions). Each block is comprised of 256 9-bit words
(one read port, one write port). The memory blocks may
be cascaded in width and/or depth to create the desired
memory organization. (Figure 2-20 on page 2-24). This
provides optimal bit widths of 9 (one block), 18, 36, and
72, and optimal depths of 256, 512, 768, and 1,024. Refer
to Actel’s SmartGen User’s Guide for more information.
Figure 2-21 on page 2-24 gives an example of optimal
memory usage. Ten blocks with 23,040 bits have been
used to generate three arrays of various widths and
depths. Figure 2-22 on page 2-24 shows how RAM blocks
can be used in parallel to create extra read ports. In this
example, using only 10 of the 88 available blocks of the
APA1000 yields an effective 6,912 bits of multiple port
RAM. The Actel SmartGen software facilitates building
wider and deeper memory configurations for optimal
memory usage.
Table 2-11 Flashlock Key Size by Device
Device
Key Size
APA075
79 bits
APA150
79 bits
APA300
79 bits
APA450
119 bits
APA600
167 bits
APA750
191 bits
APA1000
263 bits
Table 2-12 ProASICPLUS Memory Configurations by Device
Device
Bottom
Top
Maximum Width
Maximum Depth
DWDW
APA075
0
12
256
108
1,536
9
APA150
0
16
256
144
2,048
9
APA300
16
256
144
2,048
9
APA450
24
256
216
3,072
9
APA600
28
256
252
3,584
9
APA750
32
256
288
4,096
9
APA1000
44
256
396
5,632
9
相关PDF资料 |
PDF描述 |
|---|---|
| APA300-FG144I | IC FPGA PROASIC+ 300K 144-FBGA |
| AGL600V5-FG144I | IC FPGA 1KB FLASH 600K 144-FBGA |
| ACM40DTAH-S189 | CONN EDGECARD 80POS R/A .156 SLD |
| ACM40DTAD-S189 | CONN EDGECARD 80POS R/A .156 SLD |
| M1AGL600V5-FGG144I | IC FPGA 1KB FLASH 600K 144-FBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| APA300-FGG144M | 制造商:Microsemi Corporation 功能描述:FPGA PROASICPLUS 300K GATES 180MHZ 0.22UM 2.5V 144FBGA - Trays |
| APA300-FGG256 | 功能描述:IC FPGA PROASIC+ 300K 256-FBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASICPLUS 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| APA300-FGG256A | 功能描述:IC FPGA PROASIC+ 300K 256-FBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASICPLUS 产品培训模块:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色产品:Cyclone? IV FPGAs 标准包装:60 系列:CYCLONE® IV GX LAB/CLB数:9360 逻辑元件/单元数:149760 RAM 位总计:6635520 输入/输出数:270 门数:- 电源电压:1.16 V ~ 1.24 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:484-BGA 供应商设备封装:484-FBGA（23x23） |
| APA300-FGG256I | 功能描述:IC FPGA PROASIC+ 300K 256-FBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASICPLUS 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| APA300-FGG256M | 制造商:Microsemi Corporation 功能描述:FPGA PROASICPLUS 300K GATES 180MHZ 0.22UM 2.5V 256FBGA - Trays |
发布紧急采购，3分钟左右您将得到回复。