收藏本站
参数资料
型号： APA300-FGG144I
厂商： Microsemi SoC
文件页数： 161/178页
文件大小： 0K
描述： IC FPGA PROASIC+ 300K 144-FBGA
标准包装： 160
系列： ProASICPLUS
RAM 位总计： 73728
输入/输出数： 100
门数： 300000
电源电压： 2.3 V ~ 2.7 V
安装类型： 表面贴装
工作温度： -40°C ~ 85°C
封装/外壳： 144-LBGA
供应商设备封装： 144-FPBGA（13x13）
ProASICPLUS Flash Family FPGAs
v5.9
2-73
Pin Description
User Pins
I/O
User Input/Output
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Input and output signal levels are
compatible
with
standard
LVTTL
and
LVCMOS
specifications. Unused I/O pins are configured as inputs
with pull-up resistors.
NC
No Connect
To maintain compatibility with other Actel ProASICPLUS
products, it is recommended that this pin not be
connected to the circuitry on the board.
GL
Global Pin
Low skew input pin for clock or other global signals. This
pin can be configured with an internal pull-up resistor.
When it is not connected to the global network or the
clock conditioning circuit, it can be configured and used
as a normal I/O.
GLMX
Global Multiplexing Pin
Low skew input pin for clock or other global signals. This
pin can be used in one of two special ways (refer to
Actel’s Using ProASICPLUS Clock Conditioning Circuits).
When the external feedback option is selected for the
PLL block, this pin is routed as the external feedback
source to the clock conditioning circuit.
In applications where two different signals access the
same global net at different times through the use of
GLMXx and GLMXLx macros, this pin will be fixed as one
of the source pins.
This pin can be configured with an internal pull-up
resistor. When it is not connected to the global network
or the clock conditioning circuit, it can be configured and
used as any normal I/O. If not used, the GLMXx pin will
be configured as an input with pull-up.
Dedicated Pins
GND
Ground
Common ground supply voltage.
VDD
Logic Array Power Supply Pin
2.5 V supply voltage.
VDDP
I/O Pad Power Supply Pin
2.5 V or 3.3 V supply voltage.
TMS
Test Mode Select
The TMS pin controls the use of boundary-scan circuitry.
This pin has an internal pull-up resistor.
TCK
Test Clock
Clock input pin for boundary scan (maximum 10 MHz). Actel
recommends adding a nominal 20 k
Ω pull-up resistor to this
pin.
TDI
Test Data In
Serial input for boundary scan. A dedicated pull-up
resistor is included to pull this pin high when not being
driven.
TDO
Test Data Out
Serial output for boundary scan. Actel recommends
adding a nominal 20k
Ω pull-up resistor to this pin.
TRST
Test Reset Input
Asynchronous,
active
low
input pin
for
resetting
boundary-scan circuitry. This pin has an internal pull-up
resistor. For more information, please refer to Power-up
Behavior of ProASICPLUS Devices application note.
Special Function Pins
RCK
Running Clock
A free running clock is needed during programming if
the programmer cannot guarantee that TCK will be
uninterrupted. If not used, this pin has an internal pull-
up and can be left floating.
NPECL
User Negative Input
Provides high speed clock or data signals to the PLL
block. If unused, leave the pin unconnected.
PPECL
User Positive Input
Provides high speed clock or data signals to the PLL
block. If unused, leave the pin unconnected.
AVDD
PLL Power Supply
Analog VDD should be VDD (core voltage) 2.5 V (nominal)
and be decoupled from GND with suitable decoupling
capacitors to reduce noise. For more information, refer
to Actel’s Using ProASICPLUS Clock Conditioning Circuits
application note. If the clock conditioning circuitry is not
used in a design, AVDD can either be left floating or tied
to 2.5 V.
AGND
PLL Power Ground
The analog ground can be connected to the system
ground. For more information, refer to Actel’s Using
ProASICPLUS Clock Conditioning Circuits application note.
If the PLLs or clock conditioning circuitry are not used in
a design, AGND should be tied to GND.
相关PDF资料
PDF描述
APA300-FG144I IC FPGA PROASIC+ 300K 144-FBGA
AGL600V5-FG144I IC FPGA 1KB FLASH 600K 144-FBGA
ACM40DTAH-S189 CONN EDGECARD 80POS R/A .156 SLD
ACM40DTAD-S189 CONN EDGECARD 80POS R/A .156 SLD
M1AGL600V5-FGG144I IC FPGA 1KB FLASH 600K 144-FBGA
相关代理商/技术参数
参数描述
APA300-FGG144M 制造商:Microsemi Corporation 功能描述:FPGA PROASICPLUS 300K GATES 180MHZ 0.22UM 2.5V 144FBGA - Trays
APA300-FGG256 功能描述:IC FPGA PROASIC+ 300K 256-FBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASICPLUS 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27）
APA300-FGG256A 功能描述:IC FPGA PROASIC+ 300K 256-FBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASICPLUS 产品培训模块:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色产品:Cyclone? IV FPGAs 标准包装:60 系列:CYCLONE® IV GX LAB/CLB数:9360 逻辑元件/单元数:149760 RAM 位总计:6635520 输入/输出数:270 门数:- 电源电压:1.16 V ~ 1.24 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:484-BGA 供应商设备封装:484-FBGA（23x23）
APA300-FGG256I 功能描述:IC FPGA PROASIC+ 300K 256-FBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASICPLUS 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27）
APA300-FGG256M 制造商:Microsemi Corporation 功能描述:FPGA PROASICPLUS 300K GATES 180MHZ 0.22UM 2.5V 256FBGA - Trays
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*