参数资料
型号: APA600-FG676
厂商: Microsemi SoC
文件页数: 135/178页
文件大小: 0K
描述: IC FPGA PROASIC+ 600K 676-FBGA
标准包装: 40
系列: ProASICPLUS
RAM 位总计: 129024
输入/输出数: 454
门数: 600000
电源电压: 2.3 V ~ 2.7 V
安装类型: 表面贴装
工作温度: 0°C ~ 70°C
封装/外壳: 676-BGA
供应商设备封装: 676-FBGA(27x27)
ProASICPLUS Flash Family FPGAs
1- 2
v5.9
ProASICPLUS Architecture
The
proprietary
ProASICPLUS
architecture
provides
granularity comparable to gate arrays.
The ProASICPLUS device core consists of a Sea-of-Tiles
(Figure 1-1). Each tile can be configured as a three-input
logic function (e.g., NAND gate, D-Flip-Flop, etc.) by
programming
the
appropriate
flash
switch
Tiles and larger functions are connected with any of the
four levels of routing hierarchy. Flash switches are
distributed
throughout
the
device
to
provide
nonvolatile, reconfigurable interconnect programming.
Flash switches are programmed to connect signal lines to
the appropriate logic cell inputs and outputs. Dedicated
high-performance lines are connected as needed for fast,
low-skew global signal distribution throughout the core.
Maximum core utilization is possible for virtually any
design.
ProASICPLUS devices also contain embedded, two-port
SRAM blocks with built-in FIFO/RAM control logic.
Programming
options
include
synchronous
or
asynchronous operation, two-port RAM configurations,
user-defined depth and width, and parity generation or
checking.
Refer
to
the
for
more
information.
Figure 1-1 The ProASICPLUS Device Architecture
Figure 1-2 Flash Switch
256x9 Two-Port SRAM
or FIFO Block
Logic Tile
256x9 Two Port SRAM
or FIFO Block
RAM Block
I/Os
Sensing
Switching
Switch In
Switch Out
Word
Floating Gate
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