参数资料
型号: APA600-FGG676
厂商: Microsemi SoC
文件页数: 105/178页
文件大小: 0K
描述: IC FPGA PROASIC+ 600K 676-FBGA
标准包装: 40
系列: ProASICPLUS
RAM 位总计: 129024
输入/输出数: 454
门数: 600000
电源电压: 2.3 V ~ 2.7 V
安装类型: 表面贴装
工作温度: 0°C ~ 70°C
封装/外壳: 676-BGA
供应商设备封装: 676-FBGA(27x27)
ProASICPLUS Flash Family FPGAs
2- 22
v5.9
Note: Each RAM block contains a multiplexer (called DMUX) for each output signal, increasing design efficiency. These DMUX cells do not
consume any core logic tiles and connect directly to high-speed routing resources between the RAM blocks. They are used when
RAM blocks are cascaded and are automatically inserted by the software tools.
Figure 2-18 Example SRAM Block Diagrams
Table 2-14 Memory Block SRAM Interface Signals
SRAM Signal
Bits
In/Out
Description
WCLKS
1
In
Write clock used on synchronization on write side
RCLKS
1
In
Read clock used on synchronization on read side
RADDR<0:7>
8
In
Read address
RBLKB
1
In
Read block select (active Low)
RDB
1
In
Read pulse (active Low)
WADDR<0:7>
8
In
Write address
WBLKB
1
In
Write block select (active Low)
DI<0:8>
9
In
Input data bits <0:8>, <8> can be used for parity In
WRB
1
In
Write pulse (active Low)
DO<0:8>
9
Out
Output data bits <0:8>, <8> can be used for parity out
RPE
1
Out
Read parity error (active High)
WPE
1
Out
Write parity error (active High)
PARODD
1
In
Selects odd parity generation/detect when High, even parity when Low
Note: Not all signals shown are used in all modes.
SRAM
(256x9)
DI <0:8>
DO <0:8>
RADDR <0:7>
WADDR <0:7>
WRB
RDB
WBLKB
RBLKB
WCLKS
RCLKS
RPE
PARODD
DI <0:8>
WADDR <0:7>
WRB
WBLKB
PARODD
WPE
SRAM
(256x9)
DI <0:8>
DO <0:8>
WADDR <0:7>
WRB
RDB
WBLKB
RBLKB
WCLKS
RPE
PARODD
WPE
RADDR <0:7>
PARODD
DI <0:8>
DO <0:8>
RADDR <0:7>
WADDR <0:7>
WRB
RDB
WBLKB
RBLKB
RCLKS
RPE
WPE
DO <0:8>
RADDR <0:7>
RDB
RBLKB
RCLKS
RPE
Sync Write
and
Sync Read
Ports
Async Write
and
Async Read
Ports
Sync Write
and
Async Read
Ports
Async Write
and
Sync Read
Ports
SRAM
(256x9)
SRAM
(256x9)
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