参数资料
| 型号： | AT25256B-XHL-T |
| 厂商： | Atmel |
| 文件页数： | 8/24页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 256KBIT 20MHZ 8TSSOP |
| 标准包装： | 1 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 256K (32K x 8) |
| 速度： | 5MHz，10MHz，20MHz |
| 接口： | SPI 3 线串行 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 剪切带 (CT) |
| 其它名称： | AT25256B-XHL-TCT |
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection.
The Atmel ? AT25128B/256B is divided into four array segments. Top quarter (1/4), top half (1/2), or all of the mem-
ory segments can be protected. Any of the data within any selected segment will therefore be read only. The block
write protection levels and corresponding status register control bits are shown in Table 3-4 .
The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the reg-
ular memory cells (e.g. WREN, t WC , RDSR)
Table 3-4.
Block Write Protect Bits.
Level
Status Register Bits
Array Addresses Protected
BP1
BP0
Atmel AT25128B
Atmel AT25256B
0
1 (1/4)
2 (1/2)
3 (All)
0
0
1
1
0
1
0
1
None
3000 – 3FFF
2000 – 3FFF
0000 – 3FFF
None
6000 – 7FFF
4000 – 7FFF
0000 – 7FFF
The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the
write protect enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is
“1”. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is “0”. When the device is
hardware write protected, writes to the Status Register, including the Block Protect bits and the WPEN bit, and the
blockprotected sections in the memory array are disabled. Writes are only allowed to sections of the memory which
are not block-protected.
Note:
When the WPEN bit is hardware write protected, it cannot be changed back to “0”, as long as the WP pin is held low
Table 3-5.
WPEN Operation
Unprotected
WPEN
0
0
1
1
X
X
WP
X
X
Low
Low
High
High
WEN
0
1
0
1
0
1
Protected Blocks
Protected
Protected
Protected
Protected
Protected
Protected
Blocks
Protected
Writable
Protected
Writable
Protected
Writable
Status Register
Protected
Writable
Protected
Protected
Protected
Writable
READ SEQUENCE (READ): Reading the AT25128B/256B via the SO pin requires the following sequence. After
the CS line is pulled low to select a device, the Read op-code is transmitted via the SI line followed by the byte
address to be read ( Table 3-6 ). Upon completion, any data on the SI line will be ignored. The data (D7 - D0) at the
specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven
high after the data comes out. The read sequence can be continued since the byte address is automatically incre-
mented and data will continue to be shifted out. When the highest address is reached, the address counter will roll
over to the lowest address allowing the entire memory to be read in one continuous read cycle.
8
Atmel AT25128B/256B
8698C–SEEPR–8/11
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