- 您现在的位置：买卖IC网 > PDF目录295111 > AT40K40LV-3EQC (ATMEL CORP) FPGA, 2304 CLBS, 40000 GATES, PQFP240 PDF资料下载
参数资料
| 型号： | AT40K40LV-3EQC |
| 厂商： | ATMEL CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 2304 CLBS, 40000 GATES, PQFP240 |
| 封装： | PLASTIC, QFP-240 |
| 文件页数： | 10/67页 |
| 文件大小： | 1589K |
| 代理商： | AT40K40LV-3EQC |
第1页第2页第3页第4页第5页第6页第7页第8页第9页当前第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页
18
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
I/O Structure
PAD
The I/O pad is the one that connects the I/O to the outside world. Note that not all I/Os
have pads: the ones without pads are called Unbonded I/Os. The number of unbonded
I/Os varies with the device size and package. These unbonded I/Os are used to perform
a variety of bus turns at the edge of the array.
PULL-UP/PULL-DOWN
Each pad has a programmable pull-up and pull-down attached to it. This supplies a
weak “1” or “0” level to the pad pin. When all other drivers are off, this control will dictate
the signal level of the pad pin.
The input stage of each I/O cell has a number of parameters that can be programmed
either as properties in schematic entry or in the I/O Pad Attributes editor in IDS.
TTL/CMOS
The threshold level can be set to either TTL/CMOS-compatible levels.
SCHMITT
A Schmitt trigger circuit can be enabled on the inputs. The Schmitt trigger is a regenera-
tive comparator circuit that adds 1V hysteresis to the input. This effectively improves the
rise and fall times (leading and trailing edges) of the incoming signal and can be useful
for filtering out noise.
DELAYS
The input buffer can be programmed to include four different intrinsic delays as specified
in the AC timing characteristics. This feature is useful for meeting data hold require-
ments for the input signal.
DRIVE
The output drive capabilities of each I/O are programmable. They can be set to FAST,
MEDIUM or SLOW (using IDS tool). The FAST setting has the highest drive capability
(20 mA at 5V) buffer and the fastest slew rate. MEDIUM produces a medium drive
(14 mA at 5V) buffer, while SLOW yields a standard (6 mA at 5V) buffer.
TRI-STATE
Theoutput of each I/O canbemade tri-state (0, 1 or Z), opensource(1or Z) oropen
drain (0 or Z) by programming an I/O’s Source Selection mux. Of course, the output can
be normal (0 or 1), as well.
SOURCE SELECTION MUX
The Source Selection mux selects the source for the output signal of an I/O, see
相关PDF资料 |
PDF描述 |
|---|---|
| AT40K40LV-3FQC | FPGA, 2304 CLBS, 40000 GATES, PQFP304 |
| AT40KEL040KW1SB | FPGA, 2304 CLBS, 50000 GATES, PQFP160 |
| AT40KEL040KZ1SB | FPGA, 2304 CLBS, 50000 GATES, PQFP256 |
| AT89C2051-12SCT/R | 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PDSO20 |
| AT89C51-24JCT/R | 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQCC44 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AT40K40LV-3EQI | 功能描述:IC FPGA 3.3V 2304 CELL 240PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:AT40K/KLV 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
| AT40K40LV-3FQC | 制造商:Atmel Corporation 功能描述:FPGA 50K GATES 2304 CELLS COMM 0.6UM 3.3V 304PQFP - Trays |
| AT40K40LV-3FQI | 功能描述:IC FPGA 3.3V 2304 CELL 304PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:AT40K/KLV 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
| AT40KAL | 制造商:未知厂家 制造商全称:未知厂家 功能描述:AT40KAL Preliminary [Updated 6/03. 38 Pages] |
| AT40KAL040KW1M | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:Military Reprogrammable FPGAs with FreeRAM |
发布紧急采购，3分钟左右您将得到回复。