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参数资料
| 型号： | AT40K40LV-3EQC |
| 厂商： | ATMEL CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 2304 CLBS, 40000 GATES, PQFP240 |
| 封装： | PLASTIC, QFP-240 |
| 文件页数： | 6/67页 |
| 文件大小： | 1589K |
| 代理商： | AT40K40LV-3EQC |
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14
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
Clocking Scheme
There are eight Global Clock buses (GCK1 - GCK8) on the AT40K/AT40KLV FPGA.
Each of the eight dedicated Global Clock buses is connected to one of the dual-use Glo-
bal Clock pins. Any clocks used in the design should use global clocks where possible:
this can be done by using Assign Pin Locks to lock the clocks to the Global Clock loca-
tions. In addition to the eight Global Clocks, there are four Fast Clocks (FCK1 - FCK4),
two per edge column of the array for PCI specification.
Each column of an array has a “Column Clock mux” and a “Sector Clock mux”.The Col-
umn Clock mux is at the top of every column of an array and the Sector Clock mux is at
every four cells. The Column Clock mux is selected from one of the eight Global Clock
buses. The clock provided to each sector column of four cells is inverted, non-inverted
or tied off to “0”, using the Sector Clock mux to minimize the power consumption in a
sector that has no clocks. The clock can either come from the Column Clock or from the
Plane 4 express bus, see Figure 10 on page 15. The extreme-left Column Clock mux
has two additional inputs, FCK1 and FCK2, to provide fast clocking to left-side I/Os. The
extreme-right Column Clock mux has two additional inputs as well, FCK3 and FCK4, to
provide fast clocking to right-side I/Os.
The register in each cell is triggered on a rising clock edge by default. Before configura-
tion on power-up, constant “0” is provided to each register’s clock pins. After
configuration on power-up, the registers either set or reset, depending on the user’s
choice.
The clocking scheme is designed to allow efficient use of multiple clocks with low clock
skew, both within a column and across the core cell array.
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相关代理商/技术参数 |
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| AT40K40LV-3EQI | 功能描述:IC FPGA 3.3V 2304 CELL 240PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:AT40K/KLV 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
| AT40K40LV-3FQC | 制造商:Atmel Corporation 功能描述:FPGA 50K GATES 2304 CELLS COMM 0.6UM 3.3V 304PQFP - Trays |
| AT40K40LV-3FQI | 功能描述:IC FPGA 3.3V 2304 CELL 304PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:AT40K/KLV 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
| AT40KAL | 制造商:未知厂家 制造商全称:未知厂家 功能描述:AT40KAL Preliminary [Updated 6/03. 38 Pages] |
| AT40KAL040KW1M | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:Military Reprogrammable FPGAs with FreeRAM |
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