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参数资料
| 型号： | AT40KEL040KZ1SB |
| 厂商： | ATMEL CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 2304 CLBS, 50000 GATES, PQFP256 |
| 封装： | MQFP-256 |
| 文件页数： | 8/42页 |
| 文件大小： | 670K |
| 代理商： | AT40KEL040KZ1SB |
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16
AT40KEL040
4155G–AERO–05/05
Set/Reset Scheme
The AT40KEL040 family reset scheme is essentially the same as the clock scheme
except that there is only one Global Reset. A dedicated Global Set/Reset bus can be
driven by any User I/O, except those used for clocking (Global Clocks or Fast Clocks).
The automatic placement tool will choose the reset net with the most connections to use
the global resources. You can change this by using an RSBUF component in your
design to indicate the global reset. Additional resets will use the express bus network.
The Global Set/Reset is distributed to each column of the array. Like Sector Clock mux,
there is Sector Set/Reset mux at every four cells. Each sector column of four cells is
set/reset by a Plane 5 express bus or Global Set/Reset using the Sector Set/Reset mux
(Figure 11 on page 17). The set/reset provided to each sector column of four cells is
either inverted or non-inverted using the Sector Reset mux.
The function of the Set/Reset input of a register is determined by a configuration bit in
each cell. The Set/Reset input of a register is active low (logic 0) by default. Setting or
Resetting of a register is asynchronous. Before configuration on power-up, a logic 1 (a
high) is provided by each register (i.e., all registers are set at power-up).
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| AT40KFL040KZ1-E | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:Rad Hard Reprogrammable FPGAs with FreeRAM |
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