参数资料
型号: AT73C224-A
厂商: Atmel
文件页数: 65/75页
文件大小: 0K
描述: IC PWR MGMT ANALOG PMAAC 32QFN
标准包装: 490
应用: 手持/移动设备
电源电压: 2.8 V ~ 5.25 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN(5x5)
包装: 托盘
AT73C224
7.7
LDO3 & LDO4
LDO3 and LDO4 are low-drop-out voltage regulators that can provide a 1.3V, 1.5V to 1.8V (step
100 mV), 2.5V to 2.8V (100 mV step) or 3.3V output voltage.
Two kinds of applications are defined: “RF” mode (high PSRR and low noise) with 100 mA max-
imum load and “Smoother” mode with 200 mA maximum load.
By default, the LDOs are configured in RF mode. If the load is higher than 100 mA, the user
should pass into Smoother mode (see the register tables in Section 6.2.8 ”LDO3 Configuration
Register” and Section 6.2.11 ”LDO4 Configuration Register” ).
An external 2.2 μF ceramic capacitor is needed for the stability of each LDO.
Table 7-7.
LDO3 and LDO4 Electrical Characteristics
Symbol
VDD3&4
I LOAD_S
I LOAD_RF
Parameter
Operating Supply Voltage
Smoother Load current
RF Load current
Conditions
In Smoother mode
In RF mode
Min
2.8
0
0
Typ
3.6
Max
5.25
200
100
Unit
V
mA
mA
Selection in LDO3_VOLT @ 18 and
VO3,
VO4
Output Voltage
LDO4_VOLT @ 1B
VDD3 > VO3 + 200mV
1.3
3.3
V
VDD4 > VO4 + 200mV
? V o
I SC
I QQ
t R
? V DC
Accuracy
Shutdown Current
Quiescent Current
Rise Time
Line Regulation Static
I LOAD =10mA
GND output
(LDO3_CFG@17 and LDO4_CFG@1A)
No load
2.8V < VDD3 < 5.25V, full load
-8
20
100
10
8
1
%
μA
μA
μs
mV
? V DC
n
Load Regulation Static
Output Noise
10 mA <I LOAD <100 mA
In RF mode
Bandwidth: [22 - 80kHz]
10
1.5
5
mV
μVrms
In RF mode:
I LOAD =100mA, 100 Hz
70
dB
PSRR
Power Supply Rejection Ratio
I LOAD =100mA, 1kHz
I LOAD =100mA, 10kHz
I LOAD =100mA, 100kHz
65
55
45
dB
dB
dB
65
6266A–PMAAC–08-Sep-08
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