参数资料
型号: AT90S8515-8PC
厂商: Atmel
文件页数: 22/112页
文件大小: 0K
描述: IC MCU 8K FLSH 8MHZ 40DIP
标准包装: 18
系列: AVR® 90S
核心处理器: AVR
芯体尺寸: 8-位
速度: 8MHz
连通性: SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 8KB(4K x 16)
程序存储器类型: 闪存
EEPROM 大小: 512 x 8
RAM 容量: 512 x 8
电压 - 电源 (Vcc/Vdd): 4 V ~ 6 V
振荡器型: 内部
工作温度: 0°C ~ 70°C
封装/外壳: 40-DIP(0.600",15.24mm)
包装: 管件
17
AT90S8515
0841G–09/01
Indirect Program Addressing,
IJMP and ICALL
Figure 18. Indirect Program Memory Addressing
Program execution continues at address contained by the Z-register (i.e., the PC is
loaded with the contents of the Z-register).
Relative Program Addressing,
RJMP and RCALL
Figure 19. Relative Program Memory Addressing
Program execution continues at address PC + k + 1. The relative address k is -2048 to
2047.
EEPROM Data Memory
The AT90S8515 contains 512 bytes of data EEPROM memory. It is organized as a sep-
arate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM
and the CPU is described on page 44, specifying the EEPROM address registers, the
EEPROM data register and the EEPROM control register.
For the SPI data downloading, see page 86 for a detailed description.
Memory Access Times
and Instruction
Execution Timing
This section describes the general access timing concepts for instruction execution and
internal memory access.
The AVR CPU is driven by the System Clock , directly generated from the external
clock crystal for the chip. No internal clock division is used.
Figure 20 shows the parallel instruction fetches and instruction executions enabled by
the Harvard architecture and the fast-access register file concept. This is the basic pipe-
lining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for
functions per cost, functions per clocks and functions per power unit.
$000
$FFF
PROGRAM MEMORY
15
0
Z-REGISTER
$000
$FFF
PROGRAM MEMORY
15
0
15
0
12 11
PC
OP
k
+1
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