参数资料
型号: AT90S8515-8PC
厂商: Atmel
文件页数: 42/112页
文件大小: 0K
描述: IC MCU 8K FLSH 8MHZ 40DIP
标准包装: 18
系列: AVR® 90S
核心处理器: AVR
芯体尺寸: 8-位
速度: 8MHz
连通性: SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 8KB(4K x 16)
程序存储器类型: 闪存
EEPROM 大小: 512 x 8
RAM 容量: 512 x 8
电压 - 电源 (Vcc/Vdd): 4 V ~ 6 V
振荡器型: 内部
工作温度: 0°C ~ 70°C
封装/外壳: 40-DIP(0.600",15.24mm)
包装: 管件
35
AT90S8515
0841G–09/01
(TCCR1A and TCCR1B). The interrupt enable/disable settings for Timer/Counter1 are
found in the Timer/Counter Interrupt Mask Register (TIMSK).
When Timer/Counter1 is externally clocked, the external signal is synchronized with the
oscillator frequency of the CPU. To assure proper sampling of the external clock, the
minimum time between two external clock transitions must be at least one internal CPU
clock period. The external clock signal is sampled on the rising edge of the internal CPU
clock.
The 16-bit Timer/Counter1 features both a high-resolution and a high-accuracy usage
with the lower prescaling opportunities. Similarly, the high prescaling opportunities make
the Timer/Counter1 useful for lower speed functions or exact timing functions with infre-
quent actions.
The Timer/Counter1 supports two Output Compare functions using the Output Compare
Register 1 A and B (OCR1A and OCR1B) as the data sources to be compared to the
Timer/Counter1 contents. The Output Compare functions include optional clearing of
the counter on compareA match and actions on the Output Compare pins on both com-
pare matches.
Timer/Counter1 can also be used as an 8-, 9- or 10-bit Pulse Width Modulator. In this
mode, the counter and the OCR1A/OCR1B registers serve as a dual, glitch-free, stand-
alone PWM with centered pulses. Refer to page 47 for a detailed description of this
function.
The Input Capture function of Timer/Counter1 provides a capture of the Timer/Counter1
contents to the Input Capture Register (ICR1), triggered by an external event on the
input capture pin (ICP). The actual capture event settings are defined by the
Timer/Counter1 Control Register (TCCR1B). In addition, the Analog Comparator can be
set to trigger the Input Capture. Refer to “Analog Comparator” on page 59 for details on
this. The ICP pin logic is shown in Figure 31.
Figure 31. ICP Pin Schematic Diagram
If the Noise Canceler function is enabled, the actual trigger condition for the capture
event is monitored over four samples and all four must be equal to activate the capture
flag.
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