参数资料
型号: AT90S8535-8PI
厂商: Atmel
文件页数: 43/127页
文件大小: 0K
描述: IC MCU 8K FLSH 8MHZ A/D IT 40DIP
标准包装: 18
系列: AVR® 90S
核心处理器: AVR
芯体尺寸: 8-位
速度: 8MHz
连通性: SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 8KB(4K x 16)
程序存储器类型: 闪存
EEPROM 大小: 512 x 8
RAM 容量: 512 x 8
电压 - 电源 (Vcc/Vdd): 4 V ~ 6 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 40-DIP(0.600",15.24mm)
包装: 管件
22
AT90S/LS8535
1041H–11/01
placed at these locations. The circuit diagram in Figure 23 shows the reset logic. Table 3
defines the timing and electrical parameters of the reset circuitry.
Figure 23. Reset Logic
Note:
1. The Power-on Reset will not work unless the supply voltage has been below V
POT
(falling).
Power-on Reset
A Power-on Reset (POR) circuit ensures that the device is reset from power-on. As
shown in Figure 23, an internal timer clocked from the Watchdog Timer oscillator pre-
vents the MCU from starting until after a certain period after V
CC has reached the Power-
on Threshold voltage (V
POT), regardless of the VCC rise time (see Figure 24).
The user can select the start-up time according to typical oscillator start-up time. The
number of WDT oscillator cycles is shown in Table 4. The frequency of the Watchdog
oscillator is voltage-dependent as shown in “Typical Characteristics” on page 107.
If the built-in start-up delay is sufficient, RESET can be connected to V
CC directly or via
an external pull-up resistor. By holding the pin low for a period after V
CC has been
applied, the Power-on Reset period can be extended. Refer to Figure 25 for a timing
example of this.
Table 3. Reset Characteristics (V
CC = 5.0V)
Symbol
Parameter
Min
Typ
Max
Units
VPOT
(1)
Power-on Reset Threshold (rising)
1.0
1.4
1.8
V
Power-on Reset Threshold (falling)
0.4
0.6
0.8
V
RST
RESET Pin Threshold Voltage
0.6 V
CC
V
t
TOUT
Reset Delay Time-out Period
FSTRT Unprogrammed
11.0
16.0
21.0
ms
t
TOUT
Reset Delay Time-out Period
FSTRT Programmed
1.0
1.1
1.2
ms
Table 4. Number of Watchdog Oscillator Cycles
FSTRT
Time-out at V
CC = 5V
Number of WDT Cycles
Programmed
1.1 ms
1K
Unprogrammed
16.0 ms
16K
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