参数资料
| 型号： | AT90S8535-8PI |
| 厂商： | Atmel |
| 文件页数： | 86/127页 |
| 文件大小： | 0K |
| 描述： | IC MCU 8K FLSH 8MHZ A/D IT 40DIP |
| 标准包装： | 18 |
| 系列： | AVR® 90S |
| 核心处理器： | AVR |
| 芯体尺寸： | 8-位 |
| 速度： | 8MHz |
| 连通性： | SPI，UART/USART |
| 外围设备： | 欠压检测/复位，POR，PWM，WDT |
| 输入/输出数： | 32 |
| 程序存储器容量： | 8KB（4K x 16） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 512 x 8 |
| RAM 容量： | 512 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 4 V ~ 6 V |
| 数据转换器： | A/D 8x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 40-DIP（0.600"，15.24mm） |
| 包装： | 管件 |
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1997 Microchip Technology Inc.
DS30272A-page 61
PIC16C71X
8.5
Interrupts
The PIC16C71X family has 4 sources of interrupt.
The interrupt control register (INTCON) records indi-
vidual interrupt requests in ag bits. It also has individ-
ual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s ag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous
registers.
Individual
interrupt
bits
are
set
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB port change inter-
rupt and the TMR0 overow interrupt ags are con-
tained in the INTCON register.
The peripheral interrupt ags are contained in the spe-
cial function registers PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function reg-
ister INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt ag bits. The interrupt ag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
Applicable Devices
710 71 711 715
Interrupt Sources
External interrupt RB0/INT
TMR0 overow interrupt
PORTB change interrupts (pins RB7:RB4)
A/D Interrupt
Note:
Individual interrupt ag bits are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs (Figure 8-19).
The latency is the same for one or two cycle instruc-
tions. Individual interrupt ag bits are set regardless of
the status of their corresponding mask bit or the GIE
bit.
Note:
For the PIC16C71
If an interrupt occurs while the Global Inter-
rupt Enable (GIE) bit is being cleared, the
GIE bit may unintentionally be re-enabled
by the user’s Interrupt Service Routine (the
RETFIE
instruction). The
events
that
would cause this to occur are:
1.
An instruction clears the GIE bit while
an interrupt is acknowledged.
2.
The program branches to the Interrupt
vector and executes the Interrupt Ser-
vice Routine.
3.
The Interrupt Service Routine com-
pletes with the execution of the RET-
FIE
instruction. This causes the GIE
bit to be set (enables interrupts), and
the program returns to the instruction
after the one which was meant to dis-
able interrupts.
Perform the following to ensure that inter-
rupts are globally disabled:
LOOP BCF
INTCON, GIE
; Disable global
;
interrupt bit
BTFSC INTCON, GIE
; Global interrupt
;
disabled?
GOTO
LOOP
; NO, try again
:
;
Yes, continue
;
with program
;
flow
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