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型号： AT90S8535-8PI
厂商： Atmel
文件页数： 90/127页
文件大小： 0K
描述： IC MCU 8K FLSH 8MHZ A/D IT 40DIP
标准包装： 18
系列： AVR® 90S
核心处理器： AVR
芯体尺寸： 8-位
速度： 8MHz
连通性： SPI，UART/USART
外围设备： 欠压检测/复位，POR，PWM，WDT
输入/输出数： 32
程序存储器容量： 8KB（4K x 16）
程序存储器类型： 闪存
EEPROM 大小： 512 x 8
RAM 容量： 512 x 8
电压 - 电源 (Vcc/Vdd)： 4 V ~ 6 V
数据转换器： A/D 8x10b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 40-DIP（0.600"，15.24mm）
包装： 管件
1997 Microchip Technology Inc.
DS30272A-page 65
PIC16C71X
8.7
Watchdog Timer (WDT)
The Watchdog Timer is as a free running on-chip RC
oscillator which does not require any external compo-
nents. This RC oscillator is separate from the RC oscil-
lator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a SLEEP instruction. Dur-
ing normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The WDT can be permanently
disabled
by
clearing
conguration
bit
WDTE
(Section 8.1).
8.7.1
WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with tempera-
ture, VDD and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
Applicable Devices
710 71 711 715
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT and
the postscaler, if assigned to the WDT, and prevent it
from timing out and generating a device RESET condi-
tion.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
8.7.2
WDT PROGRAMMING CONSIDERATIONS
It should also be taken into account that under worst
case conditions (VDD = Min., Temperature = Max., and
max. WDT prescaler) it may take several seconds
before a WDT time-out occurs.
Note:
When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
FIGURE 8-20: WATCHDOG TIMER BLOCK DIAGRAM
FIGURE 8-21: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2007h
Cong. bits
(1)
BODEN(1)
CP1
CP0
PWRTE(1)
WDTE
FOSC1
FOSC0
81h,181h
OPTION
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Figure 8-1, Figure 8-2 and Figure 8-3 for operation of these bits.
From TMR0 Clock Source
(Figure 6-6)
To TMR0 (Figure 6-6)
Postscaler
WDT Timer
WDT
Enable Bit
0
1
M
U
X
PSA
8 - to - 1 MUX
PS2:PS0
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION register.
8
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