参数资料
型号: ATMEGA649V-8AUR
厂商: Atmel
文件页数: 100/146页
文件大小: 0K
描述: IC AVR MCU FLASH 64K 1.8V 64TQFP
产品培训模块: megaAVR Introduction
标准包装: 1,000
系列: AVR® ATmega
核心处理器: AVR
芯体尺寸: 8-位
速度: 8MHz
连通性: SPI,UART/USART,USI
外围设备: 欠压检测/复位,LCD,POR,PWM,WDT
输入/输出数: 53
程序存储器容量: 64KB(32K x 16)
程序存储器类型: 闪存
EEPROM 大小: 2K x 8
RAM 容量: 4K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-TQFP
包装: 带卷 (TR)
其它名称: ATMEGA649V-8AUR-ND
ATMEGA649V-8AURTR
PIC16(L)F1825/1829
DS41440C-page 340
2010-2012 Microchip Technology Inc.
DECFSZ
Decrement f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Operands:
0
f 127
d
[0,1]
Operation:
(f) - 1
(destination);
skip if result = 0
Status Affected:
None
Description:
The contents of register ‘f’ are decre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, then a
NOP is executed instead, making it a
2-cycle instruction.
GOTO
Unconditional Branch
Syntax:
[ label ]
GOTO k
Operands:
0
k 2047
Operation:
k
PC<10:0>
PCLATH<6:3>
PC<14:11>
Status Affected:
None
Description:
GOTO is an unconditional branch. The
eleven-bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTO is a two-cycle instruction.
INCF
Increment f
Syntax:
[ label ]
INCF f,d
Operands:
0
f 127
d
[0,1]
Operation:
(f) + 1
(destination)
Status Affected:
Z
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’, the
result is placed back in register ‘f’.
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ]
INCFSZ f,d
Operands:
0
f 127
d
[0,1]
Operation:
(f) + 1
(destination),
skip if result = 0
Status Affected:
None
Description:
The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, a NOP is
executed instead, making it a 2-cycle
instruction.
IORLW
Inclusive OR literal with W
Syntax:
[ label ]
IORLW k
Operands:
0
k 255
Operation:
(W) .OR. k
(W)
Status Affected:
Z
Description:
The contents of the W register are
OR’ed with the eight-bit literal ‘k’. The
result is placed in the W register.
IORWF
Inclusive OR W with f
Syntax:
[ label ]
IORWF
f,d
Operands:
0
f 127
d
[0,1]
Operation:
(W) .OR. (f)
(destination)
Status Affected:
Z
Description:
Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’, the
result is placed back in register ‘f’.
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