参数资料
型号: ATMEGA649V-8AUR
厂商: Atmel
文件页数: 7/146页
文件大小: 0K
描述: IC AVR MCU FLASH 64K 1.8V 64TQFP
产品培训模块: megaAVR Introduction
标准包装: 1,000
系列: AVR® ATmega
核心处理器: AVR
芯体尺寸: 8-位
速度: 8MHz
连通性: SPI,UART/USART,USI
外围设备: 欠压检测/复位,LCD,POR,PWM,WDT
输入/输出数: 53
程序存储器容量: 64KB(32K x 16)
程序存储器类型: 闪存
EEPROM 大小: 2K x 8
RAM 容量: 4K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-TQFP
包装: 带卷 (TR)
其它名称: ATMEGA649V-8AUR-ND
ATMEGA649V-8AURTR
15
2552K–AVR–04/11
ATmega329/3290/649/6490
6.7
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
CPU, directly generated from the selected clock source for the
chip. No internal clock division is used.
Figure 6-4 shows the parallel instruction fetches and instruction executions enabled by the Har-
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 6-4.
The Parallel Instruction Fetches and Instruction Executions
Figure 6-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 6-5.
Single Cycle ALU Operation
6.8
Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section “Memory Program-
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 49. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1
T2
T3
T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1
T2
T3
T4
clk
CPU
相关PDF资料
PDF描述
ATMEGA649V-8MUR MCU AVR 64KB FLASH 8MHZ 64QFN
D38999/20JA98PN CONN RCPT 3POS WALL MNT W/PINS
V48A15E500BF3 CONVERTER MOD DC/DC 15V 500W
MS27508E14F37S CONN RCPT 37POS BOX MNT W/SCKT
V48A15E500BF2 CONVERTER MOD DC/DC 15V 500W
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