参数资料
型号: ATMEGA649V-8AUR
厂商: Atmel
文件页数: 25/146页
文件大小: 0K
描述: IC AVR MCU FLASH 64K 1.8V 64TQFP
产品培训模块: megaAVR Introduction
标准包装: 1,000
系列: AVR® ATmega
核心处理器: AVR
芯体尺寸: 8-位
速度: 8MHz
连通性: SPI,UART/USART,USI
外围设备: 欠压检测/复位,LCD,POR,PWM,WDT
输入/输出数: 53
程序存储器容量: 64KB(32K x 16)
程序存储器类型: 闪存
EEPROM 大小: 2K x 8
RAM 容量: 4K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-TQFP
包装: 带卷 (TR)
其它名称: ATMEGA649V-8AUR-ND
ATMEGA649V-8AURTR
2010-2012 Microchip Technology Inc.
DS41440C-page 273
PIC16(L)F1825/1829
25.6.2
CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
releases the SCLx pin (SCLx allowed to float high).
When the SCLx pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCLx pin is actually sampled high. When the
SCLx pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPxADD<7:0> and
begins counting. This ensures that the SCLx high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
FIGURE 25-25:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
25.6.3
WCOL STATUS FLAG
If the user writes the SSPxBUF when a Start, Restart,
Stop, Receive or Transmit sequence is in progress, the
WCOL bit is set and the contents of the buffer are
unchanged (the write does not occur). Any time the
WCOL bit is set it indicates that an action on SSPxBUF
was attempted while the module was not Idle.
SDAx
SCLx
SCLx deasserted but slave holds
DX
1
DX
BRG
SCLx is sampled high, reload takes
place and BRG starts its count
03h
02h
01h
00h (hold off)
03h
02h
Reload
BRG
Value
SCLx low (clock arbitration)
SCLx allowed to transition high
BRG decrements on
Q2 and Q4 cycles
Note:
Because queueing of events is not
allowed, writing to the lower five bits of
SSPxCON2 is disabled until the Start
condition is complete.
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