ATTINY2313A-SUR (Atmel) PDF资料下载 Datasheet(34/172 页)

您现在的位置：买卖IC网 > PDF目录3777 > ATTINY2313A-SUR (Atmel)MCU AVR 2KB FLASH 20MHZ 20SOIC PDF资料下载

参数资料

129

8246B–AVR–09/11

ATtiny2313A/4313

contains data to be transmitted that has not yet been moved into the Shift Register. For compat-

ibility with future devices, always write this bit to zero when writing the UCSRA Register.

When the Data Register Empty Interrupt Enable (UDRIE) bit in UCSRB is written to one, the

USART Data Register Empty Interrupt will be executed as long as UDRE is set (provided that

global interrupts are enabled). UDRE is cleared by writing UDR. When interrupt-driven data

transmission is used, the Data Register Empty interrupt routine must either write new data to

UDR in order to clear UDRE or disable the Data Register Empty interrupt, otherwise a new inter-

rupt will occur once the interrupt routine terminates.

The Transmit Complete (TXC) flag bit is set one when the entire frame in the Transmit Shift Reg-

ister has been shifted out and there are no new data currently present in the transmit buffer. The

TXC flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be

cleared by writing a one to its bit location. The TXC flag is useful in half-duplex communication

interfaces (like the RS-485 standard), where a transmitting application must enter receive mode

and free the communication bus immediately after completing the transmission.

When the Transmit Compete Interrupt Enable (TXCIE) bit in UCSRB is set, the USART Transmit

Complete Interrupt will be executed when the TXC flag becomes set (provided that global inter-

rupts are enabled). When the transmit complete interrupt is used, the interrupt handling routine

does not have to clear the TXC flag, this is done automatically when the interrupt is executed.

14.6.4

Parity Generator

The Parity Generator calculates the parity bit for the serial frame data. When parity bit is enabled

(UPM1 = 1), the transmitter control logic inserts the parity bit between the last data bit and the

first stop bit of the frame that is sent.

14.6.5

Disabling the Transmitter

The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongo-

ing and pending transmissions are completed, i.e., when the Transmit Shift Register and

Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter

will no longer override the TxD pin.

相关代理商/技术参数	参数描述
ATTINY2313V	制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:8-bit Microcontroller with 2K Bytes In-System Programmable Flash
ATTINY2313V_06	制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:8-bit Microcontroller with 2K Bytes In-System Programmable Flash
ATtiny2313V-10MI	功能描述:8位微控制器 -MCU AVR 2K FLSH 128B EE 128B SRAM 1 UART RoHS:否制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
ATtiny2313V-10MU	功能描述:8位微控制器 -MCU 2kB Flash 0.128kB EEPROM 18 I/O Pins RoHS:否制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
ATTINY2313V-10MUR	功能描述:8位微控制器 -MCU AVR 2KFL 128B EE1.8V 128B 1UART 20P-10MHz RoHS:否制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT

发布紧急采购，3分钟左右您将得到回复。

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购