参数资料
型号: ATTINY43U-MUR
厂商: Atmel
文件页数: 12/158页
文件大小: 0K
描述: MCU AVR 4KB FLASH 8MHZ 20QFN
产品培训模块: tinyAVR Introduction
标准包装: 6,000
系列: AVR® ATtiny
核心处理器: AVR
芯体尺寸: 8-位
速度: 8MHz
连通性: USI
外围设备: 欠压检测/复位,POR,PWM,温度传感器,WDT
输入/输出数: 16
程序存储器容量: 4KB(2K x 16)
程序存储器类型: 闪存
EEPROM 大小: 64 x 8
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 4x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 20-WFQFN 裸露焊盘
包装: 带卷 (TR)
109
8048C–AVR–02/12
ATtiny43U
14.4
Alternative USI Usage
The flexible design of the USI allows it to be used for other tasks when serial communication is
not needed. Below are some examples.
14.4.1
Half-Duplex Asynchronous Data Transfer
Using the USI Data Register in three-wire mode it is possible to implement a more compact and
higher performance UART than by software, only.
14.4.2
4-Bit Counter
The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the
counter is clocked externally, both clock edges will increment the counter value.
14.4.3
12-Bit Timer/Counter
Combining the 4-bit USI counter with one of the 8-bit timer/counters creates a 12-bit counter.
14.4.4
Edge Triggered External Interrupt
By setting the counter to maximum value (F) it can function as an additional external interrupt.
The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This feature
is selected by the USICS1 bit.
14.4.5
Software Interrupt
The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.
14.5
Register Descriptions
14.5.1
USICR – USI Control Register
The Control Register includes interrupt enable control, wire mode setting, Clock Select setting,
and clock strobe.
Bit 7 – USISIE: Start Condition Interrupt Enable
Setting this bit to one enables the Start Condition detector interrupt. If there is a pending inter-
rupt when the USISIE and the Global Interrupt Enable Flag is set to one, this will immediately be
executed. See the USISIF bit description in “Analog Comparator” on page 114 for further details.
Bit 6 – USIOIE: Counter Overflow Interrupt Enable
Setting this bit to one enables the Counter Overflow interrupt. If there is a pending interrupt when
the USIOIE and the Global Interrupt Enable Flag is set to one, this will immediately be executed.
See the USIOIF bit description in “Analog Comparator” on page 114 for further details.
Bits 5:4 – USIWM[1:0]: Wire Mode
These bits set the type of wire mode to be used. Basically only the function of the outputs are
affected by these bits. Data and clock inputs are not affected by the mode selected and will
always have the same function. The counter and Shift Register can therefore be clocked exter-
Bit
7
6
5
4
3
2
1
0
USISIE
USIOIE
USIWM1
USIWM0
USICS1
USICS0
USICLK
USITC
USICR
Read/Write
R/W
W
Initial Value
0
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