参数资料
型号: ATTINY43U-MUR
厂商: Atmel
文件页数: 81/158页
文件大小: 0K
描述: MCU AVR 4KB FLASH 8MHZ 20QFN
产品培训模块: tinyAVR Introduction
标准包装: 6,000
系列: AVR® ATtiny
核心处理器: AVR
芯体尺寸: 8-位
速度: 8MHz
连通性: USI
外围设备: 欠压检测/复位,POR,PWM,温度传感器,WDT
输入/输出数: 16
程序存储器容量: 4KB(2K x 16)
程序存储器类型: 闪存
EEPROM 大小: 64 x 8
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 4x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 20-WFQFN 裸露焊盘
包装: 带卷 (TR)
29
8048C–AVR–02/12
ATtiny43U
Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system
clock. These bits can be written run-time to vary the clock frequency to suit the application
requirements. As the divider divides the master clock input to the MCU, the speed of all synchro-
nous peripherals is affected. The division factors are given in Table 6-9.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed,
the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to
“0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock
source has a higher frequency than the maximum frequency of the device at the present operat-
ing conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8
Fuse setting. The Application software must ensure that a sufficient division factor is chosen if
the selected clock source has a higher frequency than the maximum frequency of the device at
the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.
To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
1.
Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bitsin
CLKPR to zero.
2.
Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.
Table 6-9.
Clock Prescaler Select
CLKPS3
CLKPS2
CLKPS1
CLKPS0
Clock Division Factor
0
000
1
0
001
2
0
010
4
0
011
8
0
100
16
0
101
32
0
110
64
0
111
128
1
000
256
1
001
Reserved
1
010
Reserved
1
011
Reserved
1
100
Reserved
1
101
Reserved
1
110
Reserved
1
111
Reserved
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