● Operation of Each Block
? AMP
This is an error amp compares the reference voltage (0.65V) with V O to drive the output Nch FET (Ron=50m Ω ). Frequency
optimization helps to realize rapid transient response, and to support the use of ceramic capacitors on the output. AMP input
voltage ranges from GND to 2.7V, while the AMP output ranges from GND to V CC . When EN is OFF, or when UVLO is active,
output goes LOW and the output of the NchFET switches OFF.
? EN
The EN block controls the regulator ’s ON/OFF state via the EN logic input pin. In the OFF position, circuit voltage is
maintained at 0 μ A, thus minimizing current consumption at standby. The FET is switched ON to enable discharge of the
NRCS pin V O , thereby draining the excess charge and preventing the IC on the load side from malfunctioning. Since no
electrical connection is required (e.g. between the V CC pin and the ESD prevention diode), module operation is independent
of the input sequence.
? UVLO
To prevent malfunctions that can occur during a momentary decrease in V CC , the UVLO circuit switches the output OFF,
and (like the EN block) discharges NRCS and V O . Once the UVLO threshold voltage (TYP3.80V) is reached, the power-on
reset is triggered and output continues.
? CURRENT LIMIT
When output is ON, the current limit function monitors the internal IC output current against the parameter value. When
current exceeds this level, the current limit module lowers the output current to protect the load IC. When the overcurrent
state is eliminated, output voltage is restored to the parameter value.
? NRCS (Non Rush Current on Start-up)
The soft start function enabled by connecting an external capacitor between the NRCS pin and ground. Output ramp-up
can be set for any period up to the time the NRCS pin reaches V FB (0.65V). During startup, the NRCS pin serves as a 20 μ
A (TYP) constant current source to charge the external capacitor. Capacitors with low susceptibility (0.001 μ F ～ 1 μ F) to
temperature are recommended, in order to assure a stable soft-start time.
? TSD (Thermal Shut down)
The shutdown (TSD) circuit automatically is latched OFF when the chip temperature exceeds the threshold temperature
after the programmed time period elapses, thus serving to protect the IC against “thermal runaway” and heat damage.
Because the TSD circuit is intended to shut down the IC only in the presence of extreme heat, it is crucial that the Tj (max)
parameter not be exceeded in the thermal design, in order to avoid potential problems with the TSD.
? VIN
The V IN line acts as the major current supply line, and is connected to the output NchFET drain. Since no electrical
connection (such as between the V CC pin and the ESD protection diode) is necessary, V IN operates independent of the input
sequence. However, since an output NchFET body diode exists between V IN and V O , a V IN -V O electric (diode) connection is
present. Note, therefore, that when output is switched ON or OFF, reverse current may flow to V IN from V O .
? PGOOD
It outputs the status of the output voltage. This is open drain pin and connects to V CC pin through the pull-up resistance
(100k Ω or so). When the output voltage range is V O × 0.9 to V O × 1.1(TYP), the status is high.
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