参数资料
| 型号： | BD3522EFV-E2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 10/21页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO ADJ 4A HTSSOP-B20 |
| 标准包装： | 2,500 |
| 稳压器拓扑结构： | 正，可调式 |
| 输出电压： | 0.65 V ~ 2.7 V |
| 输入电压： | 0.7 V ~ 5.5 V |
| 稳压器数量： | 1 |
| 电流 - 输出： | 4A（最小） |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-HTSSOP-B |
| 包装： | 带卷 (TR) |
● Operation of Each Block
? AMP
This is an error amp compares the reference voltage (0.65V) with V O to drive the output Nch FET (Ron=50m Ω ). Frequency
optimization helps to realize rapid transient response, and to support the use of ceramic capacitors on the output. AMP input
voltage ranges from GND to 2.7V, while the AMP output ranges from GND to VCC. When EN is OFF, or when UVLO is
active, output goes LOW and the output of the NchFET switches OFF.
? EN
The EN block controls the regulator ’s ON/OFF state via the EN logic input pin. In the OFF position, circuit voltage is
maintained at 0 μ A, thus minimizing current consumption at standby. The FET is switched ON to enable discharge of the
NRCS pin V O , thereby draining the excess charge and preventing the IC on the load side from malfunctioning. Since no
electrical connection is required (e.g. between the VCC pin and the ESD prevention diode), module operation is
independent of the input sequence.
? V CC UVLO
To prevent malfunctions that can occur during a momentary decrease in V CC , the UVLO circuit switches the output OFF,
and (like the EN block) discharges NRCS and V O . Once the UVLO threshold voltage (TYP3.80V) is reached, the power-on
reset is triggered and output continues.
? V D UVLO
V D pin is the V IN voltage detect pin. When V D voltage exceeds the threshold voltage, V D UVLO becomes active. Once active,
the status of output voltage remains ON even if V D voltage drops. (When V IN voltage drops, SCP engages and output
switches OFF.) Unlike EN and V CC , it is effective at output startup. V D UVLO can be restored either by reconnecting the EN
pin or V CC pin.
? CURRENT LIMIT
When output is ON, the current limit function monitors the internal IC output current against the parameter value. When
current exceeds this level, the current limit module lowers the output current to protect the load IC. When the overcurrent
state is eliminated, output voltage is restored to the parameter value. However when output voltage falls to or below the
SCP startup voltage, the SCP function becomes active and the output switches OFF.
? NRCS (Non Rush Current on Start-up)
The soft start function enabled by connecting an external capacitor between the NRCS pin and ground. Output ramp-up
can be set for any period up to the time the NRCS pin reaches V FB (0.65V). During startup, the NRCS pin serves as a 20 μ
A (TYP) constant current source to charge the external capacitor. Output start time is calculated via the formula below.
T NRCS (typ.) =
C NRCS × V FB
I NRCS
? TSD (Thermal Shut down)
The shutdown (TSD) circuit automatically is latched OFF when the chip temperature exceeds the threshold temperature
after the programmed time period elapses, thus serving to protect the IC against “thermal runaway” and heat damage.
Because the TSD circuit is intended to shut down the IC only in the presence of extreme heat, it is crucial that the Tj (max)
parameter not be exceeded in the thermal design, in order to avoid potential problems with the TSD.
T TSD (typ.) =
C SCP × V SCPTH
20uA
? V IN
The V IN line acts as the major current supply line, and is connected to the output NchFET drain. Since no electrical
connection (such as between the V CC pin and the ESD protection diode) is necessary, V IN operates independent of the input
sequence. However, since an output NchFET body diode exists between V IN and V O , a V IN -V O electric (diode) connection is
present. Note, therefore, that when output is switched ON or OFF, reverse current may flow to V IN from V O .
? SCP
When output voltage (Vo) drops, the IC assumes that V O pin is shorted to GND and switched the output voltage OFF. After
the GND short has been detected and the programmed delay time has elapsed, output is latched OFF. It is also effective
during output startup. SCP can be cleared either by reconnecting the EN pin or V CC pin. Delay time is calculated via the
formula below.
T SCP (typ.) =
C SCP × V SCPTH
I SCP
10/20
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