参数资料
| 型号： | BD3522EFV-E2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 19/21页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO ADJ 4A HTSSOP-B20 |
| 标准包装： | 2,500 |
| 稳压器拓扑结构： | 正，可调式 |
| 输出电压： | 0.65 V ~ 2.7 V |
| 输入电压： | 0.7 V ~ 5.5 V |
| 稳压器数量： | 1 |
| 电流 - 输出： | 4A（最小） |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-HTSSOP-B |
| 包装： | 带卷 (TR) |
11. Regarding input pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode
or transistor. For example, the relation between each potential is as follows:
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes operate,
such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used.
Resistor
Transistor (NPN)
Pin A
Pin B
C
B
Pin B
Pin A
E
N
P +
N
P
P +
N
P substrate
Parasitic
element
N
P +
N
P
P +
N
P substrate
B
C
E
Parasitic
element
Parasitic element
GND
Parasitic element
GND
GND
GND
Other adjacent elements
Example of IC structure
12. Ground Wiring Pattern.
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing
a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations
caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND
wiring pattern of any external components, either.
● Heat Dissipation Characteristics
◎ HTSSOP-B20
4
70mm × 70mm × 1.6mm (PCB with Thermal Via)
3
2
1
④ 3.2W
③ 2.31W
② 1.45W
① 1W
① 1 layer substrate (substrate surface copper foil area:0mm × 0mm)
θ j-a=125 ℃ /W
② 2 layer substrate (substrate surface copper foil area:15mm × 15mm)
θ j-a=86.2 ℃ /W
③ 2 layer substrate (substrate surface copper foil area:15mm × 15mm)
θ j-a=54.1 ℃ /W
④ 4 layer substrate (substrate surface copper foil area:70mm × 70mm)
θ j-a=39.1 ℃ /W
0
25
50
75
100
125
150
Ambient Temperature:Ta [ ℃ ]
(HTSSOP-B20)
19/20
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