参数资料
型号: BR24L08FVJ-WE2
厂商: Rohm Semiconductor
文件页数: 5/41页
文件大小: 0K
描述: IC EEPROM 8KBIT 100KHZ TSSOP-B8J
标准包装: 2,500
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 8K (1K x 8)
速度: 400kHz
接口: I²C,2 线串口
电源电压: 1.8 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-VSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-TSSOP
包装: 带卷 (TR)
BR24L □□ -W Series,BR24S □□□ -W Series
● Sync data input / output timing
Technical Note
SCL
tR
tF
tHIGH
SCL
tHD:STA
tSU:DAT
tLOW
tHD:DAT
tSU:STA
tHD:STA
tSU:STO
SDA
(input)
(入力)
SDA
tBUF
tPD
tDH
SDA
(出力)
(output)
○ Input read at the rise edge of SCL
○ Data output in sync with the fall of SCL
Fig.1-(a) Sync data input / output timing
SCL
START BIT
Fig.1-(b) Start-stop bit timing
STOP BIT
SCL
DATA(1)
DATA(n)
SDA
D0
ACK
SDA
D1
D0
ACK
ACK
t WR
Write data
( n-th address )
t W R
Stop condition
Start condition
WP
tSU : WP
ト ッ プ コ ンデ ィ シ
ス Stop condition ョン
t HD : WP
SCL
Fig.1-(c) Write cycle timing
Fig.1-(d) WP timing at write execution
DATA(1)
DATA(n)
SDA
D1
D0
ACK
ACK
tHIGH:WP
tWR
WP
At write execution, in the area from the D0 taken clock rise of the first
DATA(1), to tWR, set WP=“LOW”.
By setting WP “HIGH” in the area, write can be cancelled.
When it is set WP=“HIGH” during tWR, write is forcibly ended, and data
of address under access is not guaranteed, therefore write it once again.
Fig.1-(e) WP timing at write cance
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? 2009 ROHM Co., Ltd. All rights reserved.
5/40
2009.09 - Rev.D
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