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参数资料
| 型号： | BU-64703B9-200 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CBGA80 |
| 封装： | CERAMIC, BGA-80 |
| 文件页数： | 10/48页 |
| 文件大小： | 405K |
| 代理商： | BU-64703B9-200 |
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18
Data Device Corporation
www.ddc-web.com
BU-64703
D-03/06-0
t1
CLOCK IN rising to DTREQ low
ALL
ns
t2
DTREQ falling to DTGRT low
ALL
s
t4
DTGRT low setup prior to CLOCK IN rising edge
ALL
ns
t6
CLOCK IN rising to DTACK low
ALL
ns
t7
Data output valid following CLOCK IN
ALL
ns
t8
DTGRT hold time following DTACK falling
ALL
ns
t10
Data output setup time prior to MEMWR low
t12
MEMWR low pulse width
t13
CLOCK IN rising to MEMWR high
ALL
ns
t15
Data output hold time following CLOCK IN rising
ALL
ns
t16
CWC (all but first data word) setup time prior to MEMWR low
20 MHz
ns
REF
DESCRIPTION
CLOCK
FREQUENCY
UNITS
TABLE FOR FIGURE 10. SSRT Mark3 DMA WRITE (BURST MODE) TIMING
t20
GBR low pulse width
16 MHz
ns
12 MHz
ns
10 MHz
ns
t21
INCMD rising following CLOCK IN rising (see Note 3)
ALL
ns
20 MHz
ns
16 MHz
ns
12 MHz
ns
10 MHz
ns
20 MHz
ns
16 MHz
ns
12 MHz
ns
10 MHz
ns
20 MHz
ns
16 MHz
ns
12 MHz
ns
10 MHz
ns
t3
CWC setup time prior to MEMWR falling for first word of burst transfer
(see Note 1)
20 MHz
ns
16 MHz
ns
12 MHz
ns
10 MHz
ns
t5
DTGRT falling to DTACK low
20 MHz
ns
16 MHz
ns
12 MHz
ns
10 MHz
ns
t9
DTACK low pulse width (based on a two data word transfer)
(see Note 2)
20 MHz
ns
16 MHz
ns
12 MHz
ns
10 MHz
ns
t11
CLOCK IN rising to MEMWR low
ALL
ns
t14
Data output and CWC hold time following MEMWR high
20 MHz
ns
16 MHz
ns
12 MHz
ns
10 MHz
ns
t17
CLOCK IN rising to DTREQ and DTACK high
ALL
ns
t18
Data output signal Tri-State following CLOCK IN rising
ALL
ns
t19
CLOCK IN rising to GBR falling edge
ALL
ns
15
10
VALUE @3.3 VOLTS
MIN
TYP
MAX
40
10
40
30
40
23
43
60
40
10
22
43
60
90
100
115
125
157
167
190
200
40
50
52.5
62.5
73.3
83.3
90
100
60
85
127
160
105
118
138
155
290
300
365
375
490
500
590
600
40
10
23
43
60
40
(1)
Assumes DTGRT is low at the time that DTREQ is asserted low. If not, then this time will increase by the amount of the DTREQ (low) - to - DTGRT (low) delay.
(2)
DTACK pulse width is 3 clock cycles per data word transfer.
(3)
Rising edge of INCMD will immediately follow the rising edge of GBR only for a broadcast message. For a non-broadcast message, the rising edge
of INCMD will occur after the mid-parity crossing of the RT status response. This additional delay time is approximately 96 clock cycles: 9.6 s at 10 MHz,
8 s at 12 MHz, 6.0 s at 16 MHz, or 4.8 s at 20 MHz.
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