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参数资料
| 型号： | BU-64703B9-200 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CBGA80 |
| 封装： | CERAMIC, BGA-80 |
| 文件页数： | 3/48页 |
| 文件大小： | 405K |
| 代理商： | BU-64703B9-200 |
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11
Data Device Corporation
www.ddc-web.com
BU-64703
D-03/06-0
0
1
0
CLK_SEL_0
16 MHz
1
20 MHz
0
10 MHz
0
CLOCK FREQUENCY
CLK_SEL_1
1
TABLE 3. CLOCK FREQUENCY SELECTION
12 MHz
maximum following after the L_BRO, T/R, SA4-0, and
WC/MC/CWC4-0 outputs have been presented valid.
PROTOCOL SELF-TEST
The SSRT Mark3 includes a comprehensive, autonomous off-
line self-test of its internal protocol logic. The test includes a com-
prehensive test of all registers, Manchester encoder and
decoders, transmitter failsafe timer, protocol logic, and the inter-
nal FIFO.
This test is completed in approximately 32,000 clock cycles.
That is, about 1.6 ms with a 20 MHz clock, 2.0 ms at 16 MHz,
2.7 ms at 12 MHz, and 3.2 ms at 10 MHz. While the SSRT
Mark3 is performing its off-line self-test, it will ignore (and
therefore not respond to) all messages received from the
1553 bus.
Unless disabled by means of the SSRT Mark3's Auto-Config fea-
ture, the protocol self-test will be performed following the SSRT
Mark3's power turn-on (i.e., when MSTCLR is released high). If
the Auto-Config feature is used and Auto-Config bit 5 is set to
logic "0", then a failure of the protocol self-test following power
turn-on will result in the SSRT Mark3 not going online. If bit 5 is
set to logic "0" and the protocol self-test passes following power
turn-on, the SSRT Mark3 will go online.
The protocol self-test will also be performed following receipt of
an Initiate self-test mode command from the 1553 bus. If an
Initiate self-test mode command is received by the SSRT Mark3,
and Auto-Config bit 5 is set to logic "0", then a failure of the pro-
tocol self-test following will result in the SSRT Mark3 going
offline.
If the protocol self-test fails: (1) the Terminal Flag bit will be
set to logic "1" in the SSRT Mark3 status word; (2) bit 8 in the
SSRT Mark3's BIT word, BIT Test Fail, will be set to logic "1";
(3) the SSRT Mark3's RTFAIL output will be asserted to logic
"0".
AUTO-CONFIGURATION
The SSRT Mark3 includes an auto-configuration feature, which
allows various optional features to be enabled or disabled. Auto-
configuration may be enabled or disabled by means of the input
signal AUTO_CFG. If AUTO_CFG is connected to logic "1", then
the auto-configure option is disabled, and the six configuration
parameters revert to their default values.
Note that the default condition for each configuration para-
meter is enabled (for the MIL-STD-1553A/B protocol selection, -
1553B is the default).
If AUTO_CFG is connected to logic "0", then the configuration
parameters are transferred over D5-D0 by means of a DMA read
data transfer. The transfer occurs during the time that the
RTACTIVE and DTACK outputs are logic "0", following MSTCLR
transitioning from logic "0" to logic "1" and a successful
DT_REQ-to-DTGRT handshake.
Note that if DTGRT is hardwired to logic "0", the handshake
process is not necessary (i.e., DTACK and RTACTIVE will both
be asserted to logic "0" one clock cycle following DT_REQ).
Each of the configuration parameters is enabled if the SSRT
Mark3 reads a value of logic "1" for the respective data bit.
The auto-configuration parameters are defined in TABLE 2.
The timing signals pertaining to Auto-Configuration mode are
illustrated in Figure 13.
CLOCK INPUT
The SSRT Mark3 may be operated from one of four clock fre-
quencies: 10, 12, 16, or 20 MHz. The selected clock frequency
must be designated by means of the input signals CLK_SEL_1
and CLK_SEL_0, as shown in TABLE 3.
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