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参数资料
| 型号： | BU-64703B9-200 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CBGA80 |
| 封装： | CERAMIC, BGA-80 |
| 文件页数： | 9/48页 |
| 文件大小： | 405K |
| 代理商： | BU-64703B9-200 |
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17
Data Device Corporation
www.ddc-web.com
BU-64703
D-03/06-0
FIGURE 9. RT - RT RECEIVE (NON-BURST-MODE) TIMING
L-BRO, T/R,
SA4-SA0
WC/MC/CWC
INCMD
DTREQ
DTGRT
DTACK
GBR
MEMWR
MEMOE
D15-D0
RT_FAIL
MSG_ERR
HS_FAIL
t1
t14
t17
t6
t2
t13
t18
PREVIOUS MSG
CWC = 1
WC / MC
ILLEGAL, SRV_RQST
SSFLAG, BUSY
VALID
t3
t5
t4
t10
t11
WC / MC
CWC = 0
1F
t8
t15
t9
t16
SINGLE
WORD
WRITE
DATA WORD
#1
SINGLE
WORD
WRITE
DATA WORD
#2
MID-PARITY
MID-SYNC
t12
1553 BUS
RX COMMAND
STATUS
TX COMMAND
DATA #1
MID-PARITY
MID-SYNC
t7
DATA #2
STATUS
(Refer to FIGURE 11)
t1
Mid-parity crossing of received command word delay to
SA4-SA0, L-BRO, T/R Bit, and WC/MC valid
ALL
s
t2
Mid-parity crossing of received command word delay to
falling edge of INCMD
ALL
s
t3
Mid-parity crossing of receive command word delay to
MSG_ERR and HS_FAIL rising
ALL
s
t4
ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from
SA4-SA0, L-BRO, T/R, and CWC/MC valid
ALL
ns
t5
RT Sub-Address, L-BRO, and T/R Bit setup time prior to INCMD low
ALL
500
ns
t6
ILLEGAL, SRV_RQST, SSFLAG, BUSY valid time following falling
edge of INCMD
ALL
300
ns
t7
RT - RT response timeout for transmitting RT.
ALL
17.5
s
t9
Mid-parity crossing of first data word to DTREQ falling edge
t10
WC/CWC data value of 1Fh held
t11
CWC valid following falling edge of DTREQ
ALL
ns
t12
RT Response time.
ALL
4
s
t13
Delay from following mid-parity of last received data word to GBR low.
(see Notes 1, 2)
ALL
4
s
t14
Mid-parity crossing of all data words, except first data word, to DTREQ
falling edge
ALL
s
t15
GBR pulse width
20 MHz
ns
REF
DESCRIPTION
CLOCK
FREQUENCY
RESPONSE TIME
UNITS
TABLE FOR FIGURE 9. RT-RT RECEIVE COMMAND TIMING (NON-BURST MODE)
t16
CWC transition to WC prior to Mid-Sync crossing of Status response.
MIN
TYP
MAX
1.5
2
1.5
400
18.5
19.5
30
6.5
7
1
100
16 MHz
ns
125
12 MHz
ns
167
10 MHz
ns
200
t17
Mid-Sync crossing of status response to RT_FAIL rising
ALL
s
1.5
t18
Mid-parity crossing of status word to INCMD rising
ALL
s
3.0
20 MHz
s
1.2
16 MHz
s
1.25
12 MHz
s
1.33
10 MHz
s
1.4
20 MHz
ns
75
16 MHz
ns
94
12 MHz
ns
125
10 MHz
ns
150
20 MHz
ns
200
16 MHz
ns
250
12 MHz
ns
333
10 MHz
ns
400
t8
Mid-parity crossing to WC/CWC value of 1Fh
ALL
s
1
(1)
Assumes that DTGRT is tied to logic “0”. If DTGRT is not connected to logic “0”, the minimum time to drive GBR active low will increase by the amount of the DTGRT
(low) - to - DTGRT (low) delay.
(2)
The transceiver delays are measured at a range of 150ns to 450ns for the receiver and 100ns to 250ns for the transmitter.
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