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| 型号： | BU-64703B9-200 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CBGA80 |
| 封装： | CERAMIC, BGA-80 |
| 文件页数： | 47/48页 |
| 文件大小： | 405K |
| 代理商： | BU-64703B9-200 |
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8
Data Device Corporation
www.ddc-web.com
BU-64703
D-03/06-0
L-BRO
T/R
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
PROM / RAM / PLD
(4Kx1)
SA1
WC/MC/CWC3
WC/MC/CWC2
SA0
WC/MC/CWC4
WC/MC/CWC1
SA4
SA3
SA2
WC/MC/CWC0
I LLEG AL
A0
D0
BU - 64703
"SSRT Mark3"
(400ns max)
FIGURE 3. SSRT Mark3 ILLEGALIZATION
HANDSHAKE FAIL
Following the assertion of DTREQ low by the SSRT Mark3, the
external subsystem has 10 s to respond by asserting DTACK to
logic "0".
If the SSRT Mark3 asserts DTREQ and the subsystem does not
respond with DTGRT in time for the SSRT Mark3 to complete a
data word transfer, the HSFAIL output will be asserted low to
inform the subsystem of the handshake failure, and bit 12 in the
internal Built-In-Test (BIT) word will be set to logic "1". If the
handshake failure occurs on a data word read transfer (for a
transmit command), the SSRT Mark3 will abort the current mes-
sage transmission. In the case of a handshake failure on a write
transfer (received command) the SSRT Mark3 will set the hand-
shake failure output and BIT word bit, and abort processing the
current message.
MESSAGE PROCESSING OPERATION
Following the receipt and transfer of a valid Command Word, the
SSRT Mark3 will attempt to perform one of the following opera-
tions: (1) transfer received 1553 data to the subsystem, (2) read
data from the subsystem for transmission on the 1553 bus, (3)
transmit status (and possibly the last command word or RT BIT
word) on the 1553 bus, and/or (4) set status word conditions.
The SSRT Mark3 responds to all non-broadcast messages to its
RT address with a 1553 Status Word.
RT ADDRESS
RT Address 4-0 (RT_AD_4 = MSB) and RT Address Parity
(RT_AD_P) should be programmed for a unique RT address and
reflect an odd parity sum. The SSRT Mark3 will not respond to
any MIL-STD-1553 commands or transfer received data from
any non-broadcast messages if an odd parity sum is not pre-
sented by RT_AD_4-0 and RT_AD_P. An address parity error will
be indicated by a low output on the RT_AD_ERR pin. The input
signal RT_AD_LAT operates a transparent latch for RTAD4-
RTAD0 and RTADP. If RT_AD_LAT is low, the output of the latch
tracks the value presented on the input pins. If RT_AD_LAT is
high, the output of the internal latch becomes latched to the val-
ues presented at the time of a low-to-high transition of
RT_AD_LAT.
RT address and RT Address Parity must be presented valid
before the mid-parity crossing of the 1553 command and held, at
least, until following the first received data word.
COMMAND ILLEGALIZATION
The SSRT Mark3 includes a provision for command illegaliza-
tion. If a command is illegalized, the SSRT Mark3 will set the
Message error bit and transmit its status word to the Bus
Controller. No data words will be transmitted in response to an
illegalized transmit command. However, data words associated
with an illegalized receive command will be written to the exter-
nal subsystem (although these transfers may be blocked using
external logic).
ILLEGAL is sampled approximately 2 s following the mid-parity
bit zero crossing of the received command word. A low on ILLE-
GAL will illegalize a particular command word and cause the
SSRT Mark3 to respond with its Message error bit set in its sta-
tus word. Command illegalization based on broadcast, T/R bit,
subaddress, and/or word count/mode code may be implemented
by means of an external PROM, PLD, or RAM device, as shown
in Figure 3.
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