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参数资料
| 型号： | BU9832GUL-WE2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 18/29页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 8KBIT SPI VCSP50L2 TR |
| 标准包装： | 3,000 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 8K (1K x 8) |
| 速度： | 5MHz |
| 接口： | SPI 串行 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-VFBGA，CSPBGA |
| 供应商设备封装： | VCSP50L2 |
| 包装： | 带卷 (TR) |
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BU9832GUL-W (8Kbit)
Datasheet
● At standby
○ Current at standby
Set CS “H”, and be sure to set SCK, SI, WP , HOLD input “L” or “H”. Do not input intermediate electric potantial.
○ Timing
As shown in Figure 39, at standby, when SCK is “H”, even if CS is fallen, SI status is not read at fall edge. SI status is
read at SCK rise edge after fall of CS . At standby and at power ON/OFF, set CS “H” status.
―――
Even if CS is fallen at SCK=SI=”H”,
SI status is not read at that edge.
―――
CS
Command start here. SI is read.
SCK
0
1
2
SI
Figure 39. Operating timing
―――
● WP cancel valid area
WP is normally fixed to “H” or “L” for use, but when WP is controlled so as to cancel write status register command and
write command, pay attention to the following WP valid timing.
While write or write status register command is executed, by setting WP = “L” in cancel valid area, command can be
cancelled. The area from command ope code before CS rise at internal automatic write start becomes the cancel valid
area. However, once write is started, any input cannot be cancelled. WP input becomes Don’t Care, and cancellation
becomes invalid.
SCK
CS
15
16
Ope Code
W P cancel invalid area
Data
tE/W
Data write time
W P cancel invalid area
Figure 40. WP valid timing (WRSR)
O pe Code
A d d res s
WP cancel invalid area
D a ta
tE /W
D a ta wr it e tim e
WP cancel invalid area
Figure 41. WP valid timing (WRITE)
―――――
● HOLD pin
By HOLD pin, command communication can be stopped temporarily (HOLD status). The HOLD pin carries out
command communications normally when it is HIGH. To get in HOLD status, at command communication, when SCK=LOW,
set the HOLD pin LOW. At HOLD status, SCK and SI become Don’t Care, and SO becomes high impedance (High-Z). To
release the HOLD status, set the HOLD pin HIGH when SCK=LOW. After that, communication can be restarted from the
point before the HOLD status. For example, when HOLD status is made after A5 address input at read, after release of
HOLD status, by starting A4 address input, read can be restarted. When in HOLD status, leave CS LOW. When it is set
CS =HIGH in HOLD status, the IC is reset, therefore communication after that cannot be restarted.
www.rohm.com
? 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
18/26
TSZ02201-0R2R0G100410-1-2
30.AUG.2012 Rev.001
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相关代理商/技术参数 |
参数描述 |
|---|---|
| BU9833GUL-W | 制造商:ROHM 制造商全称:Rohm 功能描述:Silicon Monolithic Integrated Circuit |
| BU9833GUL-W_10 | 制造商:ROHM 制造商全称:Rohm 功能描述:WL-CSP EEPROM family I2C BUS |
| BU9833GUL-WE2 | 功能描述:IC EEPROM 2KBIT 100KHZ VCSP50L1 RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:2,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 异步 存储容量:256K (32K x 8) 速度:15ns 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:28-TSSOP（0.465"，11.8mm 宽） 供应商设备封装:28-TSOP 包装:带卷 (TR) 其它名称:71V256SA15PZGI8 |
| BU9844GUL-W | 制造商:ROHM 制造商全称:Rohm 功能描述:WL-CSP EEPROM family I2C BUS |
| BU9844GUL-W_10 | 制造商:ROHM 制造商全称:Rohm 功能描述:WL-CSP EEPROM family I2C BUS |
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