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参数资料
| 型号： | BU9832GUL-WE2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 19/29页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 8KBIT SPI VCSP50L2 TR |
| 标准包装： | 3,000 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 8K (1K x 8) |
| 速度： | 5MHz |
| 接口： | SPI 串行 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-VFBGA，CSPBGA |
| 供应商设备封装： | VCSP50L2 |
| 包装： | 带卷 (TR) |
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BU9832GUL-W (8Kbit)
● Method to cancel each command
○ READ
Datasheet
? Method to cancel : cancel by CS = “H”
Ope code
8 bits
Address
8 bits
Data
8 bits
Cancel available in all areas of read mode
Figure 42. READ cancel valid timing
○ RDSR
? Method to cancel : cancel by CS = “H”
Ope code
8 bits
Data
8 bits
Cancel available in all
areas of rdsr mode
Figure 43. RDSR cancel valid timing
○ WRITE, PAGE WRITE
a: Ope code, address input area.
Cancellation is available by CS =”H”
b: Data input area (D7 to D1 input area)
Ope code
8bits
a
Address
8bits
Data(n)
8bits
b
tE/W
d
Cancellation is available by CS =”H”
c: Data input area (D0 area)
When CS is started, write starts.
After CS rise, cancellation cannot be made by any means.
d: tE/W area.
Cancellation is available by CS = “H”. However, when write
starts ( CS is started) in the area c, cancellation cannot be
SCK
c
Figure 44. WRITE cancel valid timing
made by any means. And by inputting on SCK clock,
SI
D7
D6
D5
D4
D3
D2
D1
D0
cancellation cannot be made. In page write mode, there is
write enable area at every 8 clocks.
b
c
Note 1)
Note 2)
If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once again.
If CS is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable, therefore,
it is necessary to fall in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or higher.
○ WRSR
a: From ope code to 15 rise.
Cancel by CS =”H”.
b: From 15 clock rise to 16 clock rise (write enable area).
When CS is started, write starts.
Ope code
SCK
SI
14
D1
a
Address
15
D0
b
16
17
c
tE/W
After CS rise, cancellation cannot be made by any means.
c: After 16 clock rise.
Cancel by CS =”H”. However, when write starts ( CS is started)
8 bits
a
8 bits
c
in the area b, cancellation cannot be made by any means.
And, by inputting on SCK clock, cancellation cannot be made.
b
Figure 45. WRSR cancel valid timing
Note 1)
Note 2)
If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once again
If CS is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable, therefore, it is
necessary to fall in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or higher.
○ WREN/WRDI
a: From ope code to clock rise, cancel by CS = “H”.
b: Cancellation is not available when CS is started after 7 clock.
SCK
7
a
8
b
9
Ope code
8 bits
a
b
Figure 46. WREN/WRDI cancel valid timing
www.rohm.com
? 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
19/26
TSZ02201-0R2R0G100410-1-2
30.AUG.2012 Rev.001
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相关代理商/技术参数 |
参数描述 |
|---|---|
| BU9833GUL-W | 制造商:ROHM 制造商全称:Rohm 功能描述:Silicon Monolithic Integrated Circuit |
| BU9833GUL-W_10 | 制造商:ROHM 制造商全称:Rohm 功能描述:WL-CSP EEPROM family I2C BUS |
| BU9833GUL-WE2 | 功能描述:IC EEPROM 2KBIT 100KHZ VCSP50L1 RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:2,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 异步 存储容量:256K (32K x 8) 速度:15ns 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:28-TSSOP（0.465"，11.8mm 宽） 供应商设备封装:28-TSOP 包装:带卷 (TR) 其它名称:71V256SA15PZGI8 |
| BU9844GUL-W | 制造商:ROHM 制造商全称:Rohm 功能描述:WL-CSP EEPROM family I2C BUS |
| BU9844GUL-W_10 | 制造商:ROHM 制造商全称:Rohm 功能描述:WL-CSP EEPROM family I2C BUS |
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