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参数资料
| 型号： | BU9844GUL-WE2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 3/29页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 16KBIT 2WIRE VCSP50L1 |
| 标准包装： | 3,000 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 16K (2K x 8) |
| 速度： | 400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 6-UFBGA，CSPBGA |
| 供应商设备封装： | VCSP50L1 |
| 包装： | 带卷 (TR) |
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BU9844GUL-W (16Kbit)
Action timing characteristics (Unless otherwise specified, Ta=-40°C to +85°C, V CC =1.7V to 5.5V)
Datasheet
FAST-MODE
STANDARD-MODE
Parameter
Symbol
2.5V ≤ V CC ≤ 5.5V
1.7V ≤ V CC ≤ 5.5V
Unit
Min. Typ. Max.
Min. Typ. Max.
SCL Frequency
Data Clock “HIGH” Time
Data Clock “LOW” Time
SDA, SCL Rise Time (Note1)
SDA< SCL Fall Time (Note1)
Start Condition Hold Time
Start Condition Setup Time
Input Data Hold Time
Input Data Setup Time
Output Data Delay Time
Output Data Hold Time
Stop Condition Setup Time
Bus Release Time Before Transfer Start
Internal Write Cycle Time
Noise Removal Valid Period (SDA, SCL terminal)
WP Hold Time
WP Setup Time
WP Valid Time
f SCL
t HIGH
t LOW
t R
t F
t HD:STA
t SU:STA
t HD:DAT
t SU:DAT
t PD
t DH
t SU:STO
t BUF
t WR
t I
t HD:WP
t SU:WP
t HIGH:WP
-
0.6
1.2
-
-
0.6
0.6
0
100
0.1
0.1
0.6
1.2
-
-
0
0.1
1.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
400
-
-
0.3
0.3
-
-
-
-
0.9
-
-
-
5
0.1
-
-
-
-
4.0
4.7
-
-
4.0
4.7
0
250
0.2
0.2
4.7
4.7
-
-
0
0.1
1.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
100
-
-
1.0
0.3
-
-
-
-
3.5
-
-
-
5
0.1
-
-
-
kHz
μ s
μ s
μ s
μ s
μ s
μ s
ns
ns
μ s
μ s
μ s
μ s
ms
μ s
ns
μ s
μ s
(Note1) Not 100% tested.
Sync Data Input / Output Timing
SCL
t R
t F
t HIGH
SCL
t HD :STA
t SU :DAT
t LOW
t HD :DAT
DATA(1)
DATA(n)
SDA
(Input)
t BUF
t PD
t DH
SDA
D1
D0
ACK
ACK
ｔ WR
SDA
(Output)
○ Input read at the rise edge of SCL
○ Data output in sync with the fall of SCL
WP
tSU ： WP
stop condition
ｔ HD ： WP
Figure 1-(a) Sync data input / output timing
SCL
SCL
Figure 1-(d) WP timing at write execution
DATA(1)
DATA(n)
tSU:STA
tHD:STA
tSU:STO
SDA
SDA
D1
D0
ACK
tHIGH:WP
ACK
tWR
WP
START BIT
STOP BIT
SCL
Figure 1-(b) Start – stop bit timing
Figure 1-(e) WP timing at write cancel
At write execution, in the area from the DO taken clock rise of the first DATA (1),
to tWR, set WP=”LOW”
By setting WP “HIGH” in the area, write can be cancelled.
When it is set WP=”HIGH” during tWR, write is forcibly ended, and data of
SDA
D0
Write data
(n-th address)
ACK
Stop condition
t WR
Start condition
address under access is not guaranteed, therefore write it once again.
Figure 1-(c) Write cycle timing
www.rohm.com
? 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
3/26
TSZ02201-0R2R0G100470-1-2
17.Sep.2013 Rev.002
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