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参数资料
| 型号： | BU99901GUZ-WE2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 3/26页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 32KBIT 2WIRE VCSP |
| 标准包装： | 3,000 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 32K (4K x 8) |
| 速度： | 400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.7 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 6-XFBGA，CSPBGA |
| 供应商设备封装： | VCSP30L1 |
| 包装： | 带卷 (TR) |
BU99901GUZ-W (32Kbit)
● Sync Data Input / Output Timing
Datasheet
SCL
tR
tF
tHIGH
SCL
(Input)
SDA
tHD :STA
tSU :DAT
tLOW
tHD :DAT
SDA
DATA(1)
D1
D0
ACK
DATA(n)
ACK
SDA
tBUF
tPD
tDH
WP
t WR
Stop condition
(Output)
○ Input read at the rise edge of SCL
○ Data output in sync with the fall of SCL
tSU ： WP
ｔ HD ： WP
Figure 1-(a). Sync data input / output timing
SCL
Figure 1-(d). WP timing at write execution
SCL
DATA(1)
DATA(n)
tSU:STA
tHD:STA
tSU:STO
SDA
D1
D0
ACK
ACK
SDA
START BIT
STOP BIT
WP
tHIGH:WP
tWR
tWR
Figure 1-(b). Start - stop bit timing
At write execution, in the area from the D0 taken clock rise of the first
DATA(1), to tWR, set WP=“LOW”.
By setting WP “HIGH” in the area, write can be cancelled.
When it is set WP=“HIGH” during tWR, write is forcibly ended, and data of
address under access is not guaranteed, therefore write it once again.
Figure 1-(e). WP timing at write cancels
SCL
SDA
D0
ACK
WRITE DATA(n)
STOP
CONDITION
t WR
START
CONDITION
Figure 1-(c). Write cycle timing
www.rohm.com
? 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
3/23
TSZ02201-0R2R0G100280-1-2
4.SEP.2012 Rev.001
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