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参数资料
| 型号： | BX80536GE2266FJ |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2260 MHz, MICROPROCESSOR, CPGA478 |
| 封装： | FLIP CHIP, MICRO PGA-478 |
| 文件页数： | 29/30页 |
| 文件大小： | 887K |
| 代理商： | BX80536GE2266FJ |
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8
Datasheet
Introduction
address bus provide a data bus bandwidth of up to 4.3 GB/second. The FSB uses Advanced
Gunning Transceiver Logic (AGTL+) signaling technology, a variant of GTL+ signaling
technology with low power enhancements.
The processor features Enhanced Intel SpeedStep Technology, which enables real-time dynamic
switching between multiple voltage and frequency points. This results in optimal performance
without compromising low power. The processor features the Auto Halt, Stop Grant, Deep Sleep,
and Deeper Sleep low power states.
The Pentium M Processor utilizes socketable Micro Flip-Chip Pin Grid Array (Micro-FCPGA) and
surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA) package technology. The Micro-
FCPGA package plugs into a 479-hole, surface-mount, zero insertion force (ZIF) socket, which is
referred to as the mPGA479M socket.
Pentium M Processors with CPU Signature = 06D8h will also include the Execute Disable Bit
capability. This feature combined with a support operating system allows memory to be marked as
executable or non executable. If code attempts to run in non-executable memory the processor
raises an error to the operating system. This feature can prevent some classes of viruses or worms
that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the
system. See the Intel Architecture Software Developer's Manual for more detailed information.
Intel will validate this feature only on Intel 915 Express chipset family-based platforms and
recommends customers implement BIOS changes related to this feature, only on Intel 915 Express
chipset family-based platforms.
Note:
The term AGTL+ is used to refer to Assisted GTL+ signalling technology on some Intel processors.
1.1
Terminology
Term
Definition
#
A “#” symbol after a signal name refers to an active low signal, indicating a signal is in
the active state when driven to a low level. For example, when RESET# is low, a reset
has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the “#” symbol implies
that the signal is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and
D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).
XXXX means that the specification or value is yet to be determined.
Front Side Bus
(FSB)
Refers to the interface between the processor and system core logic (also known as
the chipset components).
相关PDF资料 |
PDF描述 |
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| BU-61580G1-190S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70 |
| BU-61580G2-190Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70 |
| BU-61580G5-150S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70 |
| BU-61580G6-170Z | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| BX80536NC1700EJ | 制造商:Intel 功能描述:MPU CELERON PROCESSOR 390 RISC 64-BIT 90NM 1.7GHZ 1.05V - Boxed Product (Development Kits) |
| BX80537T5500 S L9SH | 制造商:Intel 功能描述:MPU Core?2 Duo Processor T5500 64-Bit 65nm 1.66GHz 1.05V 478-Pin FCPGA6 |
| BX80537T5500 S L9U4 | 制造商:Intel 功能描述:MPU Core?2 Duo Processor T5500 64-Bit 65nm 1.66GHz 1.05V 478-Pin uFCPGA |
| BX80537T5600 S L9SG | 制造商:Intel 功能描述:MPU Core?2 Duo Processor T5600 64-Bit 65nm 1.83GHz 1.05V 478-Pin FCPGA6 |
| BX80537T5600 S L9U3 | 制造商:Intel 功能描述:MPU Core?2 Duo Processor T5600 64-Bit 65nm 1.83GHz 1.05V 478-Pin uFCPGA |
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