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| 型号： | BX80536GE2266FJ |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2260 MHz, MICROPROCESSOR, CPGA478 |
| 封装： | FLIP CHIP, MICRO PGA-478 |
| 文件页数： | 3/30页 |
| 文件大小： | 887K |
| 代理商： | BX80536GE2266FJ |
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Datasheet
11
Low Power Features
2
Low Power Features
2.1
Clock Control and Low Power States
The Pentium M Processor supports the AutoHALT, Stop Grant, Sleep, Deep Sleep, and Deeper
Sleep states for optimal power management. See Figure 2-1 for a visual representation of the
processor low-power states.
2.1.1
Normal State
This is the normal operating state for the processor.
2.1.2
AutoHALT Powerdown State
AutoHALT is a low-power state entered when the processor executes the HALT instruction. The
processor will transition to the Normal state upon the occurrence of SMI#, INIT#, LINT[1:0]
(NMI, INTR), or FSB interrupt message. RESET# will cause the processor to immediately
initialize itself.
A system management interrupt (SMI) handler will return execution to either Normal state or the
AutoHALT Powerdown state. See the Intel Architecture Software Developer's Manual, Volume III:
System Programmer's guide for more information.
The system can generate a STPCLK# while the processor is in the AutoHALT Powerdown state.
When the system deasserts the STPCLK# interrupt, the processor will return execution to the
HALT state.
While in AutoHALT Powerdown state, the processor will process bus snoops and interrupts.
Figure 2-1. Clock Control States
snoop
occurs
Stop
Grant
Normal
Sleep
HALT/
Grant
Snoop
Auto Halt
Deep
Sleep
STPCLK# asserted
SLP# asserted
SLP# de-asserted
STPCLK# de-asserted
snoop
serviced
HLT
instruction
snoop
serviced
snoop
occurs
DPSLP#
de-asserted
DPSLP#
asserted
STPCLK#
asserted
STPCLK#
de-asserted
halt
break
V0001-04
core voltage raised
core voltage lowered
Halt break - A20M#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt
Deeper
Sleep
相关PDF资料 |
PDF描述 |
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| BU-61580G1-190S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70 |
| BU-61580G2-190Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70 |
| BU-61580G5-150S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70 |
| BU-61580G6-170Z | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70 |
| BU-61580S0-140Z | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| BX80536NC1700EJ | 制造商:Intel 功能描述:MPU CELERON PROCESSOR 390 RISC 64-BIT 90NM 1.7GHZ 1.05V - Boxed Product (Development Kits) |
| BX80537T5500 S L9SH | 制造商:Intel 功能描述:MPU Core?2 Duo Processor T5500 64-Bit 65nm 1.66GHz 1.05V 478-Pin FCPGA6 |
| BX80537T5500 S L9U4 | 制造商:Intel 功能描述:MPU Core?2 Duo Processor T5500 64-Bit 65nm 1.66GHz 1.05V 478-Pin uFCPGA |
| BX80537T5600 S L9SG | 制造商:Intel 功能描述:MPU Core?2 Duo Processor T5600 64-Bit 65nm 1.83GHz 1.05V 478-Pin FCPGA6 |
| BX80537T5600 S L9U3 | 制造商:Intel 功能描述:MPU Core?2 Duo Processor T5600 64-Bit 65nm 1.83GHz 1.05V 478-Pin uFCPGA |
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