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参数资料
| 型号： | BX80552641T |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 3200 MHz, MICROPROCESSOR, PBGA775 |
| 封装： | FLIP CHIP, LGA-775 |
| 文件页数： | 19/108页 |
| 文件大小： | 3283K |
| 代理商： | BX80552641T |
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20
Datasheet
Electrical Specifications
2.4
Reserved, Unused, and TESTHI Signals
All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS, VTT, or
to any other signal (including each other) can result in component malfunction or incompatibility
with future processors. See Chapter 4 for a land listing of the processor and the location of all
RESERVED lands.
In a system level design, on-die termination has been included by the processor to allow signals to
be terminated within the processor silicon. Most unused GTL+ inputs should be left as no connects
as GTL+ termination is provided on the processor silicon. However, see Table 2-6 for details on
GTL+ signals that do not include on-die termination.
Unused active high inputs, should be connected through a resistor to ground (VSS). Unused outputs
can be left unconnected, however this may interfere with some TAP functions, complicate debug
probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional
signals to power or ground. When tying any signal to power or ground, a resistor will also allow for
system testability. Resistor values should be within ± 20% of the impedance of the motherboard
trace for front side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the
TAP, GTL+ Asynchronous inputs, and GTL+ Asynchronous outputs do not include on-die
termination. Inputs and utilized outputs must be terminated on the motherboard. Unused outputs
may be terminated on the motherboard or left unconnected. Note that leaving unused outputs
unterminated may interfere with some TAP functions, complicate debug probing, and prevent
boundary scan testing.
All TESTHI[13:0] lands should be individually connected to VTT via a pull-up resistor which
matches the nominal trace impedance.
The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below.
A matched resistor must be used for each group:
TESTHI[1:0]
TESTHI[7:2]
TESTHI8 – cannot be grouped with other TESTHI signals
TESTHI9 – cannot be grouped with other TESTHI signals
TESTHI10 – cannot be grouped with other TESTHI signals
TESTHI11 – cannot be grouped with other TESTHI signals
TESTHI12 – cannot be grouped with other TESTHI signals
TESTHI13 – cannot be grouped with other TESTHI signals
However, using boundary scan test will not be functional if these lands are connected together. For
optimum noise margin, all pull-up resistor values used for TESTHI[13:0] lands should have a
resistance value within ± 20% of the impedance of the board transmission line traces. For example,
if the nominal trace impedance is 50
Ω, then a value between 40 Ω and 60 Ω should be used.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| BX80552641T2 | 制造商:Intel 功能描述:P4 641 3.2GHZ LP-BTX 2MB - Boxed Product (Development Kits) |
| BX80552651T2 | 制造商:Intel 功能描述:P4 651 3.4GHZ LP-BTX 2MB - Boxed Product (Development Kits) |
| BX80552651T2 S L94W | 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? 4 Processor 651 65nm 3.4GHz 775-Pin FCLGA6 |
| BX80552651T2 S L9KE | 制造商:Intel 功能描述:MPU Pentium |
| BX80552661T2 | 制造商:Intel 功能描述:P4 661 3.6GHZ LP-BTX 2MB - Boxed Product (Development Kits) |
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