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参数资料
| 型号： | BXM80526B700 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 700 MHz, MICROPROCESSOR, CPGA495 |
| 封装： | MICRO, PGA2-495 |
| 文件页数： | 14/85页 |
| 文件大小： | 795K |
| 代理商： | BXM80526B700 |
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Mobile Intel Pentium III Processor in BGA2 and Micro-PGA2 Packages
at 850 MHz, 800 MHz, 750 MHz, 700 MHz, and Low-voltage 600 MHz
Order#-XXX
Datasheet
13
Table 7. Recommended Resistors for Mobile Pentium III Processor Signals
Recommended
Resistor Value (
)
Mobile Pentium III Processor Signal
1, 2
No pull-up
GHI#
3
10 pull-down
BREQ0#
4
56.2 pull-up
RESET#
5
150 pull-up
PICD[1:0], TDI, TDO
270 pull-up
SMI#
680 pull-up
STPCLK#
1K pull-up
INIT#, TCK, TMS
1K pull-down
TRST#
1.5K pull-up
A20M#, FERR#, FLUSH#, IERR#, IGNNE#, LINT0/INTR,
LINT1/NMI, PREQ#, PWRGOOD, SLP#
NOTES:
1.
The recommendations above are only for signals that are being used. These recommendations are maximum values only;
stronger pull-ups may be used. Pull-ups for the signals driven by the chipset should not violate the chipset specification.
Refer to Section 3.1.4 for the required pull-up or pull-down resistors for signals that are not being used.
2.
Open-drain signals must never violate the undershoot specification in Section 4.3. Use stronger pull-ups if there is too
much undershoot.
3.
GHI# has an on-die pull-up to VCCT.
4.
A pull-down on BREQ0# is an alternative to having the central agent to drive BREQ0# low at reset.
5.
A 56.2
1% terminating resistor connected to V
CCT is required.
3.1.1 Power Sequencing Requirements
The mobile Pentium III processor has no power sequencing requirements. Intel recommends that
all of the processor power planes rise to their specified values within one second of each other.
The VCC power plane must not rise too fast. At least 200 sec (TR) must pass from the time that
VCC is at 10% of its nominal value until the time that VCC is at 90% of its nominal value (see
Figure 4. Vcc Ramp Rate Requirement
Vcc
Volts
90% Vcc (nominal)
10% Vcc (nominal)
TR
Time
3.1.2 Test Access Port (TAP) Connection
The TAP interface is an implementation of the IEEE 1149.1 (“JTAG”) standard. Due to the
voltage levels supported by the TAP interface, Intel recommends that the mobile Pentium III
processor and the other 1.5-V JTAG specification compliant devices be last in the JTAG chain
after any devices with 3.3-V or 5.0-V JTAG interfaces within the system. A translation buffer
should be used to reduce the TDO output voltage of the last 3.3/5.0V device down to the 1.5V
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