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参数资料
| 型号： | BXM80526B700 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 700 MHz, MICROPROCESSOR, CPGA495 |
| 封装： | MICRO, PGA2-495 |
| 文件页数： | 17/85页 |
| 文件大小： | 795K |
| 代理商： | BXM80526B700 |
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Mobile Intel Pentium III Processor in BGA2 and Micro-PGA2 Packages
at 850 MHz, 800 MHz, 750 MHz, 700 MHz, and Low-voltage 600 MHz
Datasheet
Order#-XXX
16
PLL section. PLL1 and PLL2 should be connected according to Figure 5. Do not connect PLL2
directly to VSS. Appendix A contains the RLC filter specification.
Figure 5. PLL RLC Filter
PLL1
PLL2
V
CCT
V0027-01
L1
C1
R1
3.3 System Bus Clock and Processor Clocking
The 2.5-V BCLK clock input directly controls the operating speed of the system bus interface. All
system bus timing parameters are specified with respect to the rising edge of the BCLK input. The
mobile Pentium III processor core frequency is a multiple of the BCLK frequency. The processor
core frequency is configured during manufacturing. The configured bus ratio is visible to software
in the Power-on configuration register, see Section 7.2 for details.
Multiplying the bus clock frequency is necessary to increase performance while allowing for
easier distribution of signals within the system. Clock multiplication within the processor is
provided by the internal Phase Lock Loop (PLL), which requires a constant frequency BCLK
input. During Reset or on exit from the Deep Sleep state, the PLL requires some amount of time to
acquire the phase of BCLK. This time is called the PLL lock latency, which is specified in
Section 3.7, AC timing parameters T18 and T47.
3.4 Intel SpeedStep Technology
The mobile Pentium III processor featuring Intel SpeedStep technology is specified to operate in
either of two modes, the “Maximum Performance Mode” or the “Battery Optimized Mode”. Each
frequency and voltage pair identifies the operating mode. The voltage provided to the processor
must meet the core voltage specification for the current operating mode. If an operating mode
transition is made, then the system logic must direct the voltage regulator to regulate to the voltage
specification of the other mode. After reset, the processor will start in the lower of its two core
frequencies, so the core voltage must meet the lower voltage specification. Any RESET# assertion
will force the processor to the lower frequency, and the core voltage must behave appropriately.
INIT# assertions ("soft" resets) and APIC bus INIT messages do not change the operating mode of
the processor. Some electrical and thermal specifications are for a specific voltage and frequency.
The mobile Pentium III processor featuring Intel SpeedStep technology will meet the electrical and
thermal specifications specific to the current operating mode and is not guaranteed to meet the
electrical and thermal specifications specific to the opposite operating mode. The timing
specifications in Table 22 must be met when performing an operating mode transition.
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