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参数资料
| 型号： | BXM80526B700 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 700 MHz, MICROPROCESSOR, CPGA495 |
| 封装： | MICRO, PGA2-495 |
| 文件页数： | 16/85页 |
| 文件大小： | 795K |
| 代理商： | BXM80526B700 |
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Mobile Intel Pentium III Processor in BGA2 and Micro-PGA2 Packages
at 850 MHz, 800 MHz, 750 MHz, 700 MHz, and Low-voltage 600 MHz
Order#-XXX
Datasheet
15
The Open-drain output signals have open drain drivers and external pull-up resistors are required.
One of the two output signals (IERR#) is a catastrophic error indicator and is tri-stated (and
pulled-up) when the processor is functioning normally. The FERR# output can be either tri-stated
or driven to VSS when the processor is in a low-power state depending on the condition of the
floating point unit. Since this signal is a DC current path when it is driven to VSS, Intel
recommends that the software clears or masks any floating-point error condition before putting the
processor into the Deep Sleep state.
3.1.5.3
Other Signals
The system bus clock (BCLK) must be driven in all of the low-power states except the Deep Sleep
state. The APIC clock (PICCLK) must be driven whenever BCLK is driven unless the APIC is
hardware disabled or the processor is in the Sleep state. Otherwise, it is permitted to turn off
PICCLK by holding it at VSS. The system bus clock should be held at VSS when it is stopped in the
Deep Sleep state.
In the Auto Halt and Stop Grant states the APIC bus data signals (PICD[1:0]) may toggle due to
APIC bus messages. These signals are required to be tri-stated and pulled-up when the processor
is in the Quick Start, Sleep, or Deep Sleep states unless the APIC is hardware disabled.
3.2 Power Supply Requirements
3.2.1 Decoupling Recommendations
The amount of bulk decoupling required on the VCC and VCCT planes to meet the voltage tolerance
requirements for the mobile Pentium III processor are a strong function of the power supply
design. Contact your Intel Field Sales Representative for tools to help determine how much bulk
decoupling is required.
For a processor with maximum performance mode at 700 MHz and above, the following
decoupling is recommended. The processor core power plane (VCC) should have fifteen 0.68 F
0603 ceramic capacitors (using X74 dielectric for thermal reasons) placed directly under the
package using two vias for power and two vias for ground to reduce the trace inductance. Also to
minimize inductance, traces to those vias should be 22mils (in width) from the capacitor pads to
match the via-pad size (assuming 22-mil pad size). Twenty-four 2.2
F 0805 mid frequency
decoupling capacitors should be placed around the die as close to the die as flex solution allows.
The system bus buffer power plane (VCCT) should have twenty 0.1-F high frequency decoupling
capacitors around the die.
For a processor with maximum performance mode at 650MHz and below, the following
decoupling is recommended. The processor core power plan (VCC) should have twelve 0.1-F high
frequency decoupling capacitors placed underneath the die and twenty-seven 0.1-
F mid
frequency decoupling capacitors placed around the die as close to the die (< 0.8” away) as flex
solution allows. The system bus buffer power plane (VCCT) should have fifteen 0.1-F high
frequency decoupling capacitors no further than 0.25 inches away from the VCCT vias (balls).
3.2.2 Voltage Planes
All VCC and VSS pins/balls must be connected to the appropriate voltage plane. All VCCT and VREF
pins/balls must be connected to the appropriate traces on the system electronics. In addition to the
main VCC, VCCT, and VSS power supply signals, PLL1 and PLL2 provide analog decoupling to the
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