参数资料
型号: BXM80526B700
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 64-BIT, 700 MHz, MICROPROCESSOR, CPGA495
封装: MICRO, PGA2-495
文件页数: 15/85页
文件大小: 795K
代理商: BXM80526B700
Mobile Intel Pentium III Processor in BGA2 and Micro-PGA2 Packages
at 850 MHz, 800 MHz, 750 MHz, 700 MHz, and Low-voltage 600 MHz
Datasheet
Order#-XXX
14
range that the mobile Pentium III processor can tolerate. Multiple copies of TMS and TRST# must
be provided, one for each voltage level.
A Debug Port and connector may be placed at the start and end of the JTAG chain containing the
processor, with TDI to the first component coming from the Debug Port and TDO from the last
component going to the Debug Port. There are no requirements for placing the mobile Pentium III
processor in the JTAG chain, except for those that are dictated by voltage requirements of the TAP
signals.
3.1.3 Catastrophic Thermal Protection
The mobile Pentium III processor does not support catastrophic thermal protection or the
THERMTRIP# signal. An external thermal sensor must be used to protect the processor and the
system against excessive temperatures.
3.1.4 Unused Signals
All signals named NC and RSVD must be unconnected. The TESTHI signal should be pulled up
to VCCT. The TESTLO1 and TESTLO2 signal should be pulled down to VSS. Unused GTL+
inputs, outputs and bi-directional signals should be unconnected. Unused CMOS active low inputs
should be connected to VCCT and unused active high inputs should be connected to VSS. Unused
Open-drain outputs should be unconnected. If the processor is configured to enter the Quick Start
state rather than the Stop Grant state, then the SLP# signal should be connected to VCCT. When
tying any signal to power or ground, a resistor will allow for system testability. For unused
signals, Intel suggests that 1.5-k
resistors are used for pull-ups and 1-k resistors are used for
pull-downs.
If the local APIC is hardware disabled, then PICCLK and PICD[1:0] should be tied to VSS with a
1-k
resistor, one resistor can be used for the three signals. Otherwise PICCLK must be driven
with a clock that meets specification (see Table 18) and the PICD[1:0] signals must be pulled up
to VCCT with 150- resistors, even if the local APIC is not used.
BSEL1 must be connected to VSS and BSEL0 must be pulled up to VCCT. VID[4:0] should be
connected to VSS if they are not used.
If the TAP signals are not used then the inputs should be pulled to ground with 1-k
resistors and
TDO should be left unconnected.
3.1.5 Signal State in Low-power States
3.1.5.1
System Bus Signals
All of the system bus signals have GTL+ input, output, or input/output drivers. Except when
servicing snoops, the system bus signals are tri-stated and pulled up by the termination resistors.
Snoops are not permitted in the Sleep and Deep Sleep states.
3.1.5.2
CMOS and Open-drain Signals
The CMOS input signals are allowed to be in either the logic high or low state when the processor
is in a low-power state. In the Auto Halt and Stop Grant states these signals are allowed to toggle.
These input buffers have no internal pull-up or pull-down resistors and system logic can use
CMOS or Open-drain drivers to drive them.
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