参数资料
型号: C8051F236-GQ
厂商: Silicon Laboratories Inc
文件页数: 141/146页
文件大小: 0K
描述: IC 8051 MCU 8K FLASH 48TQFP
产品培训模块: Serial Communication Overview
标准包装: 250
系列: C8051F2xx
核心处理器: 8051
芯体尺寸: 8-位
速度: 25MHz
连通性: SPI,UART/USART
外围设备: 欠压检测/复位,POR,WDT
输入/输出数: 32
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
RAM 容量: 1.25K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 3.6 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 48-TQFP
包装: 托盘
产品目录页面: 623 (CN2011-ZH PDF)
其它名称: 336-1244
C8051F2xx
94
Rev. 1.6
Disable WDT
Writing 0xDE followed by 0xAD to the WDTCN register disables the WDT. The following code segment
illustrates disabling the WDT.
CLR
EA
; disable all interrupts
MOV
WDTCN,#0DEh
; disable watchdog timer
MOV
WDTCN,#0ADh
;
SETB
EA
; re-enable interrupts
The writes of 0xDE and 0xAD must occur within 4 clock cycles of each other, or the disable operation is
ignored. Interrupts should be disabled during this procedure to avoid delay between the two writes.
Disable WDT Lockout
Writing 0xFF to WDTCN locks out the disable feature. Once locked out, the disable operation is ignored
until the next system reset. Writing 0xFF does not enable or reset the watchdog timer. Applications alays
intending to use the watchdog should write 0xFF to WDTCN in their initialization code.
Setting WDT Interval
WDTCN.[2:0] control the watchdog timeout interval. The interval is given by the following equation:
43+WDTCN[2:0] x TSYSCLK , (where TSYSCLK is the system clock period).
For a 2.0 MHz system clock, this provides an interval range of 32msec to 524msec. WDTCN.7 must be
written as 0 when setting this interval. Reading WDTCN returns the programmed interval. WDTCN.[2:0] is
111b after a system reset.
SFR Definition 12.1. WDTCN: Watchdog Timer Control
Bits7–0: WDT Control
Writing 0xA5 both enables and reloads the WDT.
Writing 0xDE followed within 4 clocks by 0xAD disables the WDT.
Writing 0xFF locks out the disable feature.
Bit4:
Watchdog Status Bit (when Read)
Reading the WDTCN.[4] bit indicates the Watchdog Timer Status.
0: WDT is inactive
1: WDT is active
Bits2–0: Watchdog Timeout Interval Bits
The WDTCN.[2:0] bits set the Watchdog Timeout Interval. When writing these bits,
WDTCN.7 must be set to 0.
R/W
Reset Value
xxxxx111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xFF
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