参数资料
| 型号： | CAT25512YI-GT3 |
| 厂商： | ON Semiconductor |
| 文件页数： | 6/16页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 512KB SPI SER 8-TSSOP |
| 标准包装： | 1 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 512K (64K x 8) |
| 速度： | 20MHz |
| 接口： | SPI 3 线串行 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 标准包装 |
| 其它名称： | CAT25512YI-GT3OSDKR |
CAT25512
WRITE OPERATIONS
The CAT25512 device powers up into a write disable
state. The device contains a Write Enable Latch (WEL)
which must be set before attempting to write to the memory
array or to the status register. In addition, the address of the
memory location(s) to be written must be outside the
protected area, as defined by BP0 and BP1 bits from the
status register.
Write Enable and Write Disable
The internal Write Enable Latch and the corresponding
Status Register WEL bit are set by sending the WREN
instruction to the CAT25512. Care must be taken to take the
CS input high after the WREN instruction, as otherwise the
Write Enable Latch will not be properly set. WREN timing
is illustrated in Figure 3. The WREN instruction must be
sent prior to any WRITE or WRSR instruction.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 4. Disabling write
operations by resetting the WEL bit, will protect the device
against inadvertent writes.
CS
SCK
SI
0
0
0
0
0
1
1
0
SO
Dashed Line = mode (1, 1)
HIGH IMPEDANCE
Figure 3. WREN Timing
CS
SCK
SI
0
0
0
0
0
1
0
0
SO
Dashed Line = mode (1, 1)
HIGH IMPEDANCE
Figure 4. WRDI Timing
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| CAT25-561JA | 功能描述:电阻器网络与阵列 560ohm 5% Concave 8resistors RoHS:否 制造商:Vishay/Thin Film 产品类型:Networks 电路类型:Divider 电阻器数量: 电阻数值:10 kOhms 容差:0.1 % 温度系数: 管脚数量:3 工作温度范围:- 55 C to + 155 C 尺寸:1.02 mm W x 3.05 mm L x 1.4 mm H 引线间隔: 端接类型:SMD/SMT 封装:Reel |
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