参数资料
| 型号： | CDB5461AU |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 8/44页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL & SOFTWARE CS5461A |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 嵌入式： | 是，MCU，8 位 |
| 已用 IC / 零件： | CS5461A |
| 主要属性： | 1 相，能量至频率输出 |
| 次要属性： | GUI、USB、SPI、Microwire 接口 |
| 已供物品： | 板 |
| 产品目录页面： | 754 (CN2011-ZH PDF) |
| 相关产品： | CS5461A-ISZR-ND - IC ENERGY METERING 1PHASE 24SSOP 598-1095-5-ND - IC ENERGY METERING 1PHASE 24SSOP |
| 其它名称： | 598-1552 |
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CS5461A
ANALOG CHARACTERISTICS (Continued)
Parameter
Symbol
Min
Typ
Max
Unit
Temperature Channel
Temperature Accuracy
T
-
±5
-
°C
Power Supplies
Power Supply Currents (Active State) I A+
I D+ (VA+ = VD+ = 5 V)
I D+ (VA+ = 5 V, VD+ = 3.3 V)
Power Consumption Active State (VA+ = VD+ = 5 V)
Stand-By State
Sleep State
PSCA
PSCD
PSCD
PC
-
-
-
-
-
-
-
1.1
2.9
1.7
21
12
8
10
-
-
-
28
16.5
-
-
mA
mA
mA
mW
mW
mW
μW
Power Supply Rejection Ratio (DC, 50 and 60 Hz)
Current Channel
PSRR
PMLO
PMHI
45
70
2.3
-
65
75
2.45
2.55
-
-
-
2.7
dB
dB
V
V
PSRR = 20 ? log ? ---------- ?
1. Applies when the HPF option is enabled.
2. Applies before system calibration.
3. All outputs unloaded. All inputs CMOS level.
4. Measurement method for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV (zero-to-peak) (60 Hz)
sinewave is imposed onto the +5 V DC supply voltage at VA+ and VD+ pins. The “+” and “-” input pins of both input
channels are shorted to AGND. Then the CS5461A is commanded to continuous conversion acquisition mode, and
digital output data is collected for the channel under test. The (zero-to-peak) value of the digital sinusoidal output
signal is determined, and this value is converted into the (zero-to-peak) value of the sinusoidal voltage (measured
in mV) that would need to be applied at the channel’s inputs, in order to cause the same digital sinusoidal output.
This voltage is then defined as Veq. PSRR is then (in dB) :
? 150 ?
? V eq ?
5. When voltage level on PFMON is sagging, and LSD bit is at 0, the voltage at which LSD bit is set to 1.
6. If the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), this is the voltage level on PFMON at
which the LSD bit can be permanently reset back to 0.
VOLTAGE REFERENCE
Parameter
Symbol
Min
Typ
Max
Unit
Reference Output
Output Voltage
VREFOUT
+2.4
+2.5
+2.6
V
Temperature Coefficient
Load Regulation
TC VREF
? V R
-
-
25
6
60
10
ppm/°C
mV
Reference Input
Input Voltage Range
Input Capacitance
Input CVF Current
VREFIN
+2.4
-
-
+2.5
4
25
+2.6
-
-
V
pF
nA
Notes: 7. The voltage at VREFOUT is measured across the temperature range. From these measurements the following
formula is used to calculate the VREFOUT Temperature Coefficient:.
( ( V R E F O V R E F O U T R E F O U T
TC
VREF
=
UT MAX - V
AVG
M IN )
( T
A
M AX
1
- T A M IN
( 1 .0
x 10
6
8
8.
Specified at maximum recommended output of 1 μA, source or sink.
DS661F3
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